3
DC Electrical Specications
Test Conditions: VCC = +5V, VEE = -5V, DGND =0V, AGND =0V, VREF HI = +1.00000V, VREF LO =AGND,
fCLOCK = 2.40MHz, RINT = 400k, CINT = 0.01F, TA = 25
oC, V
IN LO = AGND, CREF = 1.0F, 5
1/
2 Digit
Compensated Mode, Unless Otherwise Specied
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage, VIL
Pins 15-25, 28
-
0.8
V
Input High Voltage, VIH
Pins 15-25, 28
2.0
-
V
Output Low Voltage, VOL
Pins 16, 18-25, IOL = 1.6mA
-
0.4
V
Output High Voltage, VOH
Pins 16, 18-25, IOH = -400A
2.4
-
V
Three-State Leakage Current,
Pins 18-25, IOL
All Digital Drivers In High Impedance State,
Parallel Mode. CS = VCC, VIN = 0V, VCC
--
±10
A
Leakage, Pins 15-17, 28, IIN
VIN = 0V, VCC
--
±1
A
Input Capacitance, CIN
Pins 15, 17-25, 28
-
5
-
pF
Pin 16
-
10
-
pF
Input Pullup Current (Pins 18-25), IPU
Pins 18-25 at DGND
SEL = DGND (Serial Modes)
--5-
A
AC Electrical Specications
TA = 0
oC to 75oC; Test Conditions: V
CC = +4.75V, VEE = -5.00V (Note 8), DGND = 0V, AGND = 0V,
VIN LO =AGND, VREF HI = +1.00000V, VREF LO = AGND, fCLOCK = 2.40MHz, RINT = 400k ,
CINT = 0.01F, VIL =0V, VIH = 4V, VOL =VOH = 1.5V, tr = tf < 10ns, 5
1/
2 Digit Compensated Mode,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CS Setup/Hold of WR, t1
0-
-
ns
WR Setup of Data In, t2
50
-
ns
WR Pulse Width, t3
150
-
ns
Data Hold After WR, t4
20
-
ns
CS Setup/Hold of RD, t5
(Note 7)
25
-
ns
RD to Data Out, t6
CL = 50pF, VO = 1.5V
-
100
ns
RD to Hi-Z State, t7
-
70
ns
WR to RD, WR to WR, tA
(Note 7)
5/fCLOCK
--
s
RD to WR, tB
(Note 7)
200
-
ns
RXD Setup of Data In, tC
(Note 7)
60
-
ns
Data Hold After EXT CLK, tD
40
-
ns
EXT CLK to DATA OUT, tE
-
300
ns
CS Setup of TXD, tf
100
-
ns
NOTES:
6. All typical values have been characterized but are not production tested.
7. Not production tested, guaranteed by design and characterization.
8. All AC characteristics are guaranteed for VCC = +5V 15%, VEE = -5V 15%, over TA = 0
oC to 75oC.
HI-7159A