參數(shù)資料
型號(hào): HI2303EVAL
廠商: Intersil Corporation
英文描述: Triple 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function
中文描述: 三8位,50 MSPS的,視頻的A / D轉(zhuǎn)換器與鉗位功能
文件頁數(shù): 9/18頁
文件大?。?/td> 162K
代理商: HI2303EVAL
9
Description of Operation
Digital Output Format
The HI2303 supports eight different output formats as
detailed in Table 2. For clarity, these formats are labeled
mode 0 to 7. The modes are selected via three control pins
labeled CTL0, CTL1 and CTL2.
The converter has a latency of five clock cycles which places
a constraint on the users ability to change the mode on the
fly without corrupting the data within the converter. Please
refer to Figure 10. The SY pin is used to control mode
changes. This is achieved by using the SY as a reset/latch
signal. The Mode is reset when the SY is asserted low.
When SY transitions from low to high the control pins are
latched internally and mode is changed per timing diagram
latency.
FIGURE 5. DIFFERENTIAL GAIN AND PHASE ERROR vs TEST CIRCUIT
FIGURE 6. DIGITAL OUTPUT TEST CIRCUIT
Test Circuits
(Continued)
NTSC
SIGNAL
SOURCE
S.G.
(CW)
A
IN
8
B
IN
C
IN
8
8
8
8
DUT
HI2303
TTL
ECL
-5.2V
620
10-BIT
D/A
VECTOR
SCOPE
CLK
-5.2V
D.G.
D.P.
HI20201
40 IRE
MODULATION
BURST
SYNC
FC
-40
0
100
I
2.5V
0.5V
TTL
ECL
620
A
B
C
AMP
A
RT
, B
AT
, C
RT
A
IN
, B
IN
, C
IN
A
RB
, B
RB
, C
RB
CLK
OE
V
SS
DATA
OUT
V
DD
V
OL
+
-
I
OL
A
2.5V
0.5V
A
RT
, B
RT
, C
RT
A
IN
, B
IN
, C
IN
A
RB
, B
RB
, C
AB
CLK
OE
V
SS
DATA
OUT
V
DD
V
OL
A
+
-
I
OL
2.5V
0.5V
TABLE 2. SETTING VALUES AND OUTPUT FORMATS
SETTING
OUTPUT
CTL2
CTL1
CTLO
MODE
FORMAT
L
L
L
0
4:4:4
L
L
H
1
4:2:2 (8F
S
)
L
H
L
2
4:2:2 (D2)
L
H
H
3
4:2:2 (Special)
H
L
L
4
4:1:1
H
L
H
5
4:1:1 (Special)
H
H
L
6
Simple Boundary, Scan 1
H
H
H
7
Simple Boundary, Scan 2
HI2303
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