參數(shù)資料
型號(hào): HI2302
廠商: Intersil Corporation
英文描述: 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function
中文描述: 8位,50 MSPS的,視頻的A / D轉(zhuǎn)換器與鉗位功能
文件頁(yè)數(shù): 4/16頁(yè)
文件大小: 167K
代理商: HI2302
4-4
DC CHARACTERISTICS
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 5V or 3.3V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
I
AD
+ I
DD
NTSC Ramp,
Wave Input,
CLE = 0V
I
DD
I
REF
R
REF
Supply Current
DV
DD
= 5V
DV
DD
= 3.3V
-
25
36
mA
Analog
I
AD
-
23
33
mA
Digital
-
2
3
mA
Reference Current
4.1
5.4
7.7
mA
Reference Resistance
(V
RT
- V
RB
)
Self-Bias Voltage
260
370
480
V
RB
Shorts V
RTS
and A
VDD
Shorts V
RBS
and A
VSS
0.52
0.56
0.60
V
V
RT -
V
RB
C
AI1
C
AI2
C
DIN
C
AO
C
DO
V
IH
V
IL
I
IH
I
IL
1.80
1.92
2.04
V
Input Capacitance
V
IN
, V
IN
= 1.5V + 0.07V
RMS
V
RTS
, V
RT
, V
RB
, V
RBS
, V
REF
TEST, CLK, CLP, CLE, OE
-
15
-
pF
-
-
11
pF
-
-
11
pF
Output Capacitance
CCP
-
-
11
pF
D0 to D7, TEST
-
-
11
pF
Digital Input Voltage
AV
DD
= 4.75 to 5.25V,
DV
DD
= 3 to 5.5V, T
A
= -20
o
C to 75
o
C
2.2
-
-
V
-
-
0.8
V
Digital Input Current
V
I
= 0V to AV
DD
,
T
A
= 20
o
C to 75
o
C
CLK
-240
-
240
μ
A
μ
A
μ
A
TEST, CLP, CLE
-240
-
40
OE
-40
-
240
Digital Output Current
I
OH
I
OL
I
OH
I
OL
OE = 0V, DV
DD
= 5V
T
A
= 20
o
C to 75
o
C
V
OH
= DV
DD
- 0.8V
V
OL
= 0.4V
V
OH
= DV
DD
- 0.8V
V
OL
= 0.4V
-
-
-2
mA
4
-
-
mA
OE = 0V
DV
DD
= 3.3V
T
A
= -20
o
C to 75
o
C
OE = 3V
DV
DD
= 3 to 5.5V
T
A
= -20
o
C to 75
o
C
-
-
-1.2
mA
2.4
-
-
mA
I
OZH
I
OZL
V
OH
= DV
DD
V
OL
= 0V
-40
-
40
μ
A
μ
A
-40
-
40
TIMING
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 5V or 3.3V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
Output Data Delay
t
PZH
CL = 15pF
OE = 0V
t
PHL
t
PLH
t
PHL
Three-State Output Enable
Time
C
L
= 15pF
OE = 3V
0V
t
PZH
t
PZL
Three-State Output Enable
Time
OE = 3V
0V
t
PZH
,t
PZL
Clamp Pulse Width
t
CPW
f
C
= 14.3MHz, C
IN
= 10
μ
F for NTSC Wave
NOTES:
2. The offset voltage E
OB
is a potential difference between V
RB
and a point of position where the voltage drops equivalent to
1
/
2
LSB of
the voltage when the output data changes from “00000000” to “00000001”. E
OT
is a potential difference between V
RT
and a potential
point where the voltage rises equivalent to
1
/
2
LSB of the voltage when the output data changes from “11111111” to “11111110”.
3. The voltage of up to (AV
DD
+ 0.5V) can be input when DV
DD
= 3.3V. But the output pin voltage is less than the DV
DD
voltage. When the
digital output is in the high impedance mode, the IC may be damaged by applying the voltage which is more than the (DV
DD
+ 0.5V)
voltage to the digital output.
4. The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) for other processing
systems to equal the values for NTSC.
DV
DD
= 5V
5.5
9.5
12.0
ns
8.5
ns
DV
DD
= 3.3V
4.3
11.8
16.3
ns
7.6
ns
t
PZH
t
PZL
R
L
= 1k
DV
DD
= 5V
2.5
4.5
8.0
ns
6.0
ns
DV
DD
= 3.3V
3.0
7.0
9.0
ns
5.0
ns
t
PHZ
, t
PLZ
R
L
= 1k
, C
L
= 15pF
DV
DD
= 5V
DV
DD
= 3.3V
3.5
5.5
7.5
ns
2.5
5.5
8.0
ns
Note 4
1.75
2.75
3.75
μ
s
Electrical Specifications
f
C
= 50 MSPS, AV
DD
= 5V, DV
DD
= 3 to 5.5V, V
RB
= 0.5V, V
RT
= 2.5V, T
A
= 25
o
C
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
NOTES
MIN
TYP
MAX
UNITS
HI2302
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