參數(shù)資料
型號: HI1177
廠商: Intersil Corporation
英文描述: 8-Bit, 40MSPS, 2-Channel D/A Converter
中文描述: 8位,40MSPS,雙通道D / A轉(zhuǎn)換
文件頁數(shù): 8/8頁
文件大?。?/td> 105K
代理商: HI1177
12
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Operation
How to select the output resistance:
- The HI1177 is a D/A converter of the current output type.
To obtain the output voltage connect the resistance to IO
pin (Y0, C0). For specifications we have:
- Calculate the output resistance value from the relation
of V
FS
= I
FS
X R. Also, 16 times resistance of the output
resistance is connected to reference current pin I
REF
. In
some cases, however, this turns out to be a value that
does not actually exist. In such a case a value close to it
can be used as a substitute. Here please note that V
FS
becomes V
FS
= V
REF
X 16R/R’. R is the resistance
connected to IO while R’ is connected to I
REF
. Increas-
ing the resistance value can curb power consumption.
On the other hand glitch energy and data settling time
will inversely increase. Set the most suitable value
according to the desired application.
Phase relation between data and clock:
- To obtain the expected performance as a D/A converter, it
is necessary to set properly the phase relation between
data and clock applied from the exterior. Be sure to
satisfy the provisions of the set up time (t
S
) and hold time
(t
H
) as stipulated in the Electrical Characteristics.
V
DD
, V
SS
:
- To reduce noise effects separate analog and digital
systems in the device periphery. For V
DD
pins, both
digital and analog, bypass respective GNDs by using a
ceramic capacitor of about 0.1
μ
F, as close as possible
to the pin.
Application Circuit
FIGURE 11.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
31
30
29
28
32
0.1
μ
F
Y OUT
C OUT
200
AV
SS
(LSB)
Y IN
DV
SS
CLOCK
3.3K
1K
C IN
(MSB)
(MSB)
(LSB)
200
AV
SS
AV
DD
AV
SS
AV
SS
AV
SS
DV
SS
0.1
μ
F
AV
DD
DV
DD
Output full scale voltage
Output full scale current
V
FS
= less than 2V
I
FS
= less than 15mA
HI1177
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