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參數(shù)資料
| 型號(hào)： | HI1175JCB |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 20 MSPS, Flash A/D Converter |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 74K |
| 代理商： | HI1175JCB |
4-1078
Detailed Description
The HI1175 is a 2-step A/D converter featuring a 4-bit upper
comparator group and two lower comparator groups of 4 bits
each. The reference voltage can be obtained from the
onboard bias generator or be supplied externally. This IC
uses an offset canceling type comparator that operates syn-
chronously with an external clock. The operating modes of
the part are input sampling (S), hold (H), and compare (C).
The operation of the part is illustrated in Figure 2. A
reference voltage that is between V
RT
-V
RB
is constantly
applied to the upper 4-bit comparator group. V
I
(1) is sam-
pled with the falling edge of the first clock by the upper com-
parator block. The lower block A also samples V
I
(1) on the
same edge. The upper comparator block finalizes compari-
son data MD(1) with the rising edge of the first clock. Simul-
taneously the reference supply generates a reference
voltage RV(1) that corresponds to the upper results and
applies it to the lower comparator block A. The lower com-
parator block finalizes comparison data LD(1) with the rising
edge of the second clock. MD(1) and LD(1) are combined
and output as OUT(1) with the rising edge of the third clock.
There is a 2.5 cycle clock delay from the analog input sam-
pling point to the corresponding digital output data. Notice
how the lower comparator blocks A and B alternate generat-
ing the lower data in order to increase the overall A/D sam-
pling rate.
Power, Grounding, and Decoupling
To reduce noise effects, separate the analog and digital
grounds.
In order to avoid latchup at power up, it is necessary that
AV
DD
and DV
DD
be driven from the same supply.
Bypass both the digital and analog V
DD
pins to their respec-
tive grounds with a ceramic 0.1
μ
F capacitor close to the pin.
Analog Input
The input capacitance is small when compared with other
flash type A/D converters. However, it is necessary to drive
the input with an amplifier with sufficient bandwidth and drive
capability. In order to prevent parasitic oscillation, it may be
necessary to insert a low value (i.e., 0.24
) resistor between
the output of the amplifier and the A/D input.
Reference Input
The range of the A/D is set by the voltage between V
RT
and
V
RB
. The internal bias generator will set V
RTS
to 2.6V and
V
RBS
to 0.6V. These can be used as the part reference by
shorting V
RT
and V
RTS
and V
RB
to V
RBS
. The analog input
range of the A/D will now be from 0.6V to 2.6V and is
referred to as Self Bias Mode 1. Self Bias Mode 2 is where
V
RB
is connected to AGND and V
RT
is shorted to V
RTS
. The
analog input range will now be from 0V to 2.4V.
Test Circuits
FIGURE 21. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT
-
+
V
IN
HI1175
DUT
8
CLK (20MHz)
A<B
COMPARATOR
A>B
A8
TO
A1
A0
B8
TO
B1
B0
“0”
“1”
8
S1
S2
-V
+V
S1 : ON IF A < B
S2 : ON IF A > B
BUFFER
DVM
CONTROLLER
8
TO
111 10
000 00
HI1175
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI1175JCB-T | 功能描述:CONV A/D 8BIT 20MSPS 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI1175JCP | 制造商:Harris Corporation 功能描述: |
| HI1176 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS, Flash A/D Converter |
| HI1176_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS, Flash A/D Converter |
| HI1176-EV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS, Flash A/D Converter |
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