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參數(shù)資料
| 型號： | HI1175JCB-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/13頁 |
| 文件大小： | 0K |
| 描述： | CONV A/D 8BIT 20MSPS 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 60mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
10
Detailed Description
The HI1175 is a 2-step A/D converter featuring a 4-bit upper
comparator group and two lower comparator groups of 4 bits
each. The reference voltage can be obtained from the
onboard bias generator or be supplied externally. This IC
uses an offset canceling type comparator that operates
synchronously with an external clock. The operating modes of
the part are input sampling (S), hold (H), and compare (C).
The operation of the part is illustrated in Figure 2. A
reference voltage that is between VRT-VRB is constantly
applied to the upper 4-bit comparator group. VI(1) is
sampled with the falling edge of the first clock by the upper
comparator block. The lower block A also samples VI(1) on
the same edge. The upper comparator block finalizes
comparison data MD(1) with the rising edge of the first clock.
Simultaneously the reference supply generates a reference
voltage RV(1) that corresponds to the upper results and
applies it to the lower comparator block A. The lower
comparator block finalizes comparison data LD(1) with the
rising edge of the second clock. MD(1) and LD(1) are
combined and output as OUT(1) with the rising edge of the
third clock. There is a 2.5 cycle clock delay from the analog
input sampling point to the corresponding digital output data.
Notice how the lower comparator blocks A and B alternate
generating the lower data in order to increase the overall A/D
sampling rate.
Power, Grounding, and Decoupling
To reduce noise effects, separate the analog and digital
grounds.
In order to avoid latchup at power up, it is necessary that
AVDD and DVDD be driven from the same supply.
Bypass both the digital and analog VDD pins to their
respective grounds with a ceramic 0.1
F capacitor close to
the pin.
Analog Input
The input capacitance is small when compared with other
flash type A/D converters. However, it is necessary to drive
the input with an amplifier with sufficient bandwidth and drive
capability. In order to prevent parasitic oscillation, it may be
necessary to insert a low value (i.e., 0.24
) resistor between
the output of the amplifier and the A/D input.
Reference Input
The range of the A/D is set by the voltage between VRT and
VRB. The internal bias generator will set VRTS to 2.6V and
VRBS to 0.6V. These can be used as the part reference by
shorting VRT and VRTS and VRB to VRBS. The analog input
range of the A/D will now be from 0.6V to 2.6V and is
referred to as Self Bias Mode 1. Self Bias Mode 2 is where
VRB is connected to AGND and VRT is shorted to VRTS.
The analog input range will now be from 0V to 2.4V.
Test Circuits
FIGURE 21. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT
-
VIN
HI1175
DUT
8
CLK (20MHz)
+
A<B
A>B
COMPARATOR
A8
A1
A0
B8
B1
B0
“0”
“1”
8
S1
S2
-V
+V
S1 : ON IF A < B
S2 : ON IF A > B
BUFFER
DVM
CONTROLLER
8
TO
111 10
000 00
TO
HI1175
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