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參數(shù)資料
| 型號： | HI1171JCB-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 8BIT 40MSPS HS 24-SOIC |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 10ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 40M |
3
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DVSS . . . . . . . . . . . . . . . . . . +7.0V
Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . +7.0V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature, Plastic Package . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = +4.75V to +5.25V, DVDD = +4.75 to +5.25V, VREF = +2.0V, fS = 40MHz,
CLK Pulse Width = 12.5ns, TA = 25
oC (Note 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution, n
-8-
Bits
Integral Linearity Error, INL
fS = 40MHz (End Point)
-0.5
-
1.3
LSB
Differential Linearity Error, DNL
fS = 40MHz
-
±0.25
LSB
Offset Error, VOS
(Note 2)
-
1
mV
Full Scale Error, FSE (Adjustable to Zero)
(Note 2)
-
±13
LSB
Full Scale Output Current, IFS
-10
15
mA
Full Scale Output Voltage, VFS
1.9
2.0
2.1
V
Output Voltage Range, VFSR
0.5
2.0
2.1
V
DYNAMIC CHARACTERISTICS
Throughput Rate
See Figure 7
40.0
-
MHz
Glitch Energy, GE
ROUT = 75
-30-
pV-s
Differential Gain,
AV (Note 3)
-
1.2
-
%
Differential Phase,
φ (Note 3)
-
0.5
-
Degree
REFERENCE INPUT
Voltage Reference Input Range
0.5
-
2.0
V
Reference Input Resistance
(Note 3)
1.0
-
M
DIGITAL INPUTS
Input Logic High Voltage, VIH
(Note 3)
3.0
-
V
Input Logic Low Voltage, VIL
(Note 3)
-
1.5
V
Input Logic Current, IIL, IIH
(Note 3)
-
±5.0
A
Digital Input Capacitance, CIN
(Note 3)
-
5.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 1
5
-
ns
Data Hold Time, tHLD
See Figure 1
10
-
ns
HI1171
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