參數(shù)資料
型號： HI1171-EV
廠商： Intersil Corporation
英文描述： VOLT REG POS 4V 100MA SMD TO-243
中文描述： 8位，40 MSPS的，高速D / A轉(zhuǎn)換
文件頁數(shù)： 3/7頁
文件大?。?/td> 42K
代理商： HI1171-EV
3
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DV
DD
to DV
SS
. . . . . . . . . . . . . . . . . . .+7.0V
Analog Supply Voltage AV
DD
to AV
SS
. . . . . . . . . . . . . . . . . .+7.0V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DD
to V
SS
V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature, Plastic Package . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
98
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= +4.75V to +5.25V, DV
DD
= +4.75 to +5.25V, V
REF
= +2.0V, f
S
= 40MHz,
CLK Pulse Width = 12.5ns, T
A
= 25
o
C (Note 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution, n
-
8
-
Bits
Integral Linearity Error, INL
f
S
= 40MHz (End Point)
-0.5
-
1.3
LSB
Differential Linearity Error, DNL
f
S
= 40MHz
-
-
±
0.25
LSB
Offset Error, V
OS
(Note 2)
-
-
1
mV
Full Scale Error, FSE (Adjustable to Zero)
(Note 2)
-
-
±
13
LSB
Full Scale Output Current, I
FS
-
10
15
mA
Full Scale Output Voltage, V
FS
1.9
2.0
2.1
V
Output Voltage Range, V
FSR
0.5
2.0
2.1
V
DYNAMIC CHARACTERISTICS
Throughput Rate
See Figure 7
40.0
-
-
MHz
Glitch Energy, GE
R
OUT
= 75
-
30
-
pV-s
Differential Gain,
A
V
(Note 3)
-
1.2
-
%
Differential Phase,
φ
(Note 3)
-
0.5
-
Degree
REFERENCE INPUT
Voltage Reference Input Range
0.5
-
2.0
V
Reference Input Resistance
(Note 3)
1.0
-
-
M
DIGITAL INPUTS
Input Logic High Voltage, V
IH
(Note 3)
3.0
-
-
V
Input Logic Low Voltage, V
IL
(Note 3)
-
-
1.5
V
Input Logic Current, I
IL
, I
IH
(Note 3)
-
-
±
5.0
μ
A
Digital Input Capacitance, C
IN
(Note 3)
-
5.0
-
pF
TIMING CHARACTERISTICS
Data Setup Time, t
SU
See Figure 1
5
-
-
ns
Data Hold Time, t
HLD
See Figure 1
10
-
-
ns
HI1171
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