參數資料
型號: HI1-774J-5
廠商: HARRIS SEMICONDUCTOR
元件分類: ADC
英文描述: Complete, 12-Bit A/D Converters with Microprocessor Interface
中文描述: 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28
文件頁數: 8/18頁
文件大小: 200K
代理商: HI1-774J-5
6-959
t
HEC
CE Pulse Width
50
-
-
ns
t
SSC
CS to CE Setup
50
-
-
ns
t
HSC
CS Low During CE High
50
-
-
ns
t
SRC
R/C to CE Setup
50
-
-
ns
t
HRC
R/C Low During CE High
50
-
-
ns
t
SAC
A
O
to CE Setup
0
-
-
ns
t
HAC
A
O
Valid During CE High
50
-
-
ns
t
C
Conversion Time
12-Bit Cycle T
MIN
to T
MAX
15
20
25
μ
s
8-Bit Cycle T
MIN
to T
MAX
10
13
17
μ
s
READ MODE
t
DD
Access Time from CE
-
75
150
ns
t
HD
Data Valid After CE Low
25
-
-
ns
t
HL
Output Float Delay
-
100
150
ns
t
SSR
CS to CE Setup
50
-
-
ns
t
SRR
R/C to CE Setup
0
-
-
ns
t
SAR
A
O
to CE Setup
50
-
-
ns
t
HSR
CS Valid After CE Low
0
-
-
ns
t
HRR
R/C High After CE Low
0
-
-
ns
t
HAR
A
O
Valid After CE Low
50
-
-
ns
t
HS
STS Delay After Data Valid
300
-
1200
ns
Timing Specifications
(HI-674A) 25
o
C, Note 2, Unless Otherwise Specified
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
t
DSC
STS Delay from CE
-
-
200
ns
t
HEC
CE Pulse Width
50
-
-
ns
t
SSC
CS to CE Setup
50
-
-
ns
t
HSC
CS Low During CE High
50
-
-
ns
t
SRC
R/C to CE Setup
50
-
-
ns
t
HRC
R/C Low During CE High
50
-
-
ns
t
SAC
A
O
to CE Setup
0
-
-
ns
t
HAC
A
O
Valid During CE High
50
-
-
ns
t
C
Conversion Time
12-Bit Cycle T
MIN
to T
MAX
9
12
15
μ
s
8-Bit Cycle T
MIN
to T
MAX
6
8
10
μ
s
READ MODE
t
DD
Access Time from CE
-
75
150
ns
t
HD
Data Valid After CE Low
25
-
-
ns
t
HL
Output Float Delay
-
100
150
ns
Timing Specifications
(HI-574A) 25
o
C, Note 2, Unless Otherwise Specified
(Continued)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
HI-574A, HI-674A, HI-774
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