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參數(shù)資料
| 型號(hào)： | HI-8020SM-64 |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | CMOS HIGH VOLTAGE DISPLAY DRIVER |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 271K |
| 代理商： | HI-8020SM-64 |
FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (
input,one bitofdataisclockedintotheshiftregisterfromthe
serial data input (DIN) with each negative transition of the
Clock (
) input.
is internally tied to VSS on some
versions. A Logic "1" present at the Load (LD) input will
cause a parallel transfer of data from the shift register to the
data latch. If the Load (LD) input is held high while data is
clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8020 and
CMOScompatibleontheHI-8120.
)
To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-of-
phasewiththebackplane.
The backplane output functions in 1 of 2 modes; externally
drivenorself-oscillating. WhentheLCDinputisexternally
driven with the LCDOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCD. Utilizing the
self-oscillating mode, inputs LCD and LCDOPT are tied
together and connected to an RC circuit (Figure 3).
A 150K
resistor with a 470pF capacitor generates an
approximate backplane frequency of 100Hz. The
LCD/LCDOPT oscillator frequency is divided by 256 to
determine the backplane output frequency.
value (R) must be at least 30K
operation.
The resistor
for proper self-oscillator
For displays having a number of segments greater than 38,
twoormoreofthedisplaydriversmaybecascadedtogether
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc.(See Figures 2 & 3). Data out (DOUT) will change state
CS
CL
CS
HI-8020/HI-8120 Series
TIMING DIAGRAM
t
CSH
t
CSS
t
DS
t
DH
t
CL
t
CDO
t
LS
t
LW
t
CSL
t
LCS
CL
INPUT
DIN
INPUT
CS
INPUT
LD
INPUT
DOUT
OUTPUT
VALID
VALID
HOLT INTEGRATED CIRCUITS
3-10
INTERNAL OSCILLATOR CIRCUIT
TO BACKPLANE
TRANSLATOR
AND DRIVER
÷ 256
C
R
LCD
OPT
LCD
Figure 1.
Q
VALID
on the rising edge of the Clock (
and Chip Select (
other,respectively,betweenallcascadeddisplaydrivers.
). Clock (
), Load (LD)
) should be tied in common with each
CL
CL
CS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI-8020SERIES | CMOS High Voltage LCD Display Driver (30-38 Segments) |
| HI-8120S-61 | CMOS HIGH VOLTAGE DISPLAY DRIVER |
| HI-8120S-63 | CMOS HIGH VOLTAGE DISPLAY DRIVER |
| HI-8120 | CMOS HIGH VOLTAGE DISPLAY DRIVER |
| HI-8120SM-62 | 256 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI-8040 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:CMOS HIGH VOLTAGE DISPLAY DRIVER |
| HI-8040_05 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:CMOS HIGH VOLTAGE DISPLAY DRIVER |
| HI-8040Q | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:CMOS HIGH VOLTAGE DISPLAY DRIVER |
| HI-8040QM-01 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:CMOS HIGH VOLTAGE DISPLAY DRIVER |
| HI-8040QT | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:CMOS HIGH VOLTAGE DISPLAY DRIVER |
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