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參數(shù)資料
| 型號： | HI-7159A |
| 廠商： | Intersil Corporation |
| 英文描述： | 128 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 微處理器兼容，5-1/2位A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 210K |
| 代理商： | HI-7159A |
2
Absolute Maximum Ratings
Thermal Information
Supply Voltage
V
CC
to GND (A
GND
/D
GND
) . . . . . . . . . . . . . . -0.3V < V
CC
< +6V
V
EE
to GND (A
GND
/D
GND
) . . . . . . . . . . . . . . +0.3V < V
CC
< -6V
Digital Pins, (pins 15 - 28) . . . . . . . . D
GND
-0.3V < V
D
<V
CC
+0.3V
Analog Pins, (pins 2 - 13). . . . . . . . . . .V
EE
-0.3V < V
A
< V
CC
+0.3V
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature, T
STG
. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
θ
JA
(
o
C/W)
50
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: V
CC
= +5V, V
EE
= -5V, D
GND
= 0V, A
GND
= 0V, V
REF HI
= +1.00000V, V
REF LO
= AGND,
f
CLOCK
= 2.40MHz, R
INT
= 400k
, C
INT
= 0.01
μ
F, T
A
= 25
o
C, V
IN LO
= A
GND
, C
REF
= 1.0
μ
F, 5
1
/
2
Digit
Compensated Mode, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Integral Non-Linearity, INL
0V to +2V (Notes 2, 3, 4, 5)
-
±
0.0015
±
0.0035
% FS
-2V to 0V (Notes 2, 3, 4, 5)
-
±
0.0015
±
0.0035
% FS
Ratiometric Reading
V
IN HI
= V
REF HI
= 1.00000V
99996
100000
100003
Counts
Zero Error, ZE
V
IN HI
= 0.00000V
-
0
±
1
Counts
Voltage Range of V
IN LO
Input
(Pin 13), V
IN LO
-2V
≤
V
IN HI
- V
IN LO
≤
2V
-1
-
1
V
Voltage Range of V
IN HI
Input
(Pin 12), V
IN HI
-2V
≤
V
IN HI
- V
IN LO
≤
2V
V
IN LO
-2V
-
V
IN LO
+2V
V
Common Mode Rejection, CMR
V
IN HI
= V
IN LO
= -3V to +3V
-
3
-
Counts
Input Leakage Current, I
IN
Pins 9, 10, 12, 13, V
IN
= +3V, -3V
-
-
±
0.1
μ
A
Input Capacitance, C
IN
Pins 9, 10, 12, 13
-
5
-
pF
Noise (Peak-to-Peak Value, Not
Exceeded 95% of Time), e
N
-
±
1
-
Counts
Zero Drift, T
C(ZE)
V
IN HI
= 0.00000V
-
0
-
Counts/
o
C
Full Scale Error Tempco, T
C(FSE)
V
IN HI
=
±
2.00000V
-
±
0.1
-
Counts/
o
C
Supply Range, V
SUPPLY
V
CC
+4.75
+5.0
+5.5
V
V
EE
-4.75
-5.0
-5.5
V
V
CC
Supply Current, I
CC
-
-
10
mA
V
EE
Supply Current, I
EE
-
-
4.5
mA
Digital GND Current, I
DGND
-
-
5.5
mA
Analog GND Current, I
AGND
-
+3
-
μ
A
V
CC
, V
EE
Power Supply Rejection,
PSR
V
IN HI
= V
REF HI
= 1.00000V, V
CC
= +4.75V,
V
EE
= -4.75V to V
CC
= +5.50V, V
EE
= -5.50V
-
3
-
Counts
Guard Driver Pins 5, 8
Output Current, I
OGD
V
IN
(Pins 9, 10) = +3V, -3V
±
10
-
-
μ
A
NOTES:
2. All typical values have been characterized but are not production tested.
3. Not production tested, guaranteed by design and characterization.
4. Reference adjusted for correct full-scale reading.
5. V
IN
= V
IN HI
- V
IN LO
.
HI-7159A
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