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參數(shù)資料
| 型號(hào)： | HI-565A |
| 廠商： | Intersil Corporation |
| 英文描述： | 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 高速，單片的D / A轉(zhuǎn)換器與參考 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 303K |
| 代理商： | HI-565A |
5
added to convert this current to a voltage. Refer to Table 2
for the voltage output case, along with Figure 1 or Figure 2.
Calibration is a two step process for each of the five output
ranges shown in Table 2. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e., affects each code by
the same amount.
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum value is the same as for integral
nonlinearity error. In general, only two values of output may
be calibrated exactly; all others must tolerate some error.
Choosing the extreme end points (plus and minus full scale)
minimizes this distributed error for all other codes.
TABLE 2. OPERATING MODES AND CALIBRATION
MODE
CIRCUIT CONNECTIONS
CALIBRATION
OUTPUT
PRANGE
PIN 10 TO
PIN 11 TO
RESlSTOR (R)
APPLY
INPUT CODE
ADJUST
TO SET
V
O
Unipolar
(See Figure 1)
0 to +10V
V
O
Pin 10
1.43K
All 0’s
All 1’s
R1
R2
0V
+9.99756V
0 to +5V
V
O
Pin 9
1.1K
All 0’s
All 1’s
R1
R2
0V
+4.99878V
Bipolar
(See Figure 2)
±
10V
NC
V
O
1.69K
All 0’s
All 1’s
R3
R4
-10V
+9.99512V
±
5V
V
O
Pin 10
1.43K
All 0’s
All 1’s
R3
R4
-5V
+4.99756V
±
2.5V
V
O
Pin 9
1.1K
All 0’s
All 1’s
R3
R4
-2.5V
+2.49878V
REF OUT
x CODE)
(4 x IREF
IO
3.5K
3K
CODE
INPUT
DAC
2.5K
5K
9
DAC
OUT
C
9.95K
5K
10
11
20V SPAN
10V SPAN
VO
R (SEE
TABLE 2)
0.5mA
IREF
HI-565A
19.95K
+
-
4
3
6
5
8
BIP.
OFF.
VCC
7
12
24
13
MSB
LSB
REF
GND
REF
IN
10V
-V
EE
PWR
GND
R2
100
+
-
+
-
+15V
-15V
100k
100
50k
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
HI-565A
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