參數(shù)資料
型號: HI-5051
廠商: Harris Corporation
英文描述: 64 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN
中文描述: 15V/-15V模擬信號范圍寬,高電流能力80mA的(典型)
文件頁數(shù): 6/11頁
文件大?。?/td> 183K
代理商: HI-5051
9-115
Specifications HI-5040 Series
I
D(ON)
, On Leakage Current
+25
o
C
-
0.01
2
-
0.01
2
nA
Full
-
2
200
-
2
200
nA
POWER REQUIREMENTS
P
D
, Quiescent Power Dissipation
+25
o
C
-
1.5
-
-
1.5
-
mW
I+, I-, I
L
, I
R
+25
o
C
-
-
0.2
-
-
0.3
mA
I+, +15V Quiescent Current
(Note 4)
Full
-
-
0.3
-
-
0.5
mA
I-, -15V Quiescent Current
(Note 4)
Full
-
-
0.3
-
-
0.5
mA
I
L
, +5V Quiescent Current
(Note 4)
Full
-
-
0.3
-
-
0.5
mA
I
R
, Ground Quiescent Current
(Note 4)
Full
-
-
0.3
-
-
0.5
mA
NOTES:
1. V
OUT
=
±
10V, I
OUT
=
A). For HI-5040 thru HI-5047
B). For HI-5048 thru HI-5051, HI-5046A/5047A.
1mA
2. V
IN
= 0V, C
L
= 10,000pF.
3. R
L
= 100
, f = 100kHz, V
IN
= 2.0V
P-P
, C
L
= 5pF.
4. V
AL
= 0V, V
AH
= 5V.
Switching Waveforms
Top: TTL Input (1V/Div.)
V
AH
= 5V, V
AL
= 0V
Bottom: Output (2V/Div.)
Horizontal: 200ns/Div.
FIGURE 1.
Top: CMOS Input (5V/Div.)
V
AH
= 10V, V
AL
= 0V
Bottom: Output (5V/Div.)
Horizontal: 200ns/Div.
FIGURE 2.
Electrical Specifications
Supplies = +15V, -15V; V
R
= 0V; V
AH
(Logic Level High) = 2.4V, V
AL
(Logic Level Low) = +0.8V, V
L
= +5V,
Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics, Unused Pins
are Grounded. (Continued)
PARAMETER
TEST
CONDITIONS
TEMP
-55
o
C To +125
o
C
0
o
C To +75
o
C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
INPUT
OUTPUT
INPUT
OUTPUT
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