參數(shù)資料
型號: HI-3583PCT-10F
廠商: HOLT INTEGRATED CIRCUITS INC
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, PQCC64
封裝: 9 X 9 MM, ROHS COMPLIANT, PLASTIC, CSP-64
文件頁數(shù): 1/15頁
文件大?。?/td> 164K
代理商: HI-3583PCT-10F
HI-3582, HI-3583
3.3V ARINC 429 TERMINAL IC
64
-
N/C
63
-
RIN2B
62
-
RIN2A
61
-
RIN1B
60
-
RIN1A
59
-
N/C
58
-
VDD
57
-
VDD
56
-
VDD
55
-
N/C
54
-
TEST
53
-
51
MR
RSR
52
-
TXCLK
-
CLK
50
-
49
-
N/C
48
47
46 - N/C
45 - V+
44 - TXBOUT
43 - TXAOUT
42 - V-
41
40 -
39 -
38 - TX/R
37 -
36 -
35 -
34 - BD01
PL1
-
-ENTX
- N/C
BD00
33 - N/C
CWSTR
FFT
HFT
PL2
N/C
-1
7
BD10
-1
8
BD09
-1
9
BD08
-2
0
BD07
-2
1
-2
2
GND
-2
3
N/C
-2
4
-2
5
-2
6
-2
7
BD05
-2
8
BD04
-
2
9
BD06
N/C
BD03
-
3
0
BD02
-3
1
N/C
-3
2
N/C - 1
-2
-3
-4
-5
-6
-7
SEL - 8
-9
-10
N/C - 11
BD15 - 12
HF1
D/R1
FF1
D/R2
FF2
HF2
EN1
EN2
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
(Note: All 3 VDD pins
be connected to the same 3.3V supply)
must
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
GENERAL DESCRIPTION
The HI-3582/HI-3583 from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-3582/HI-3583 design offers many enhancements to the
industry standard HI-8282 architecture. The device
provides two receivers each with label recognition, 32 by
32 FIFO, and analog line receiver. Up to 16 labels may be
programmed for each receiver. The independent transmit-
ter has a 32 X 32 FIFO and a built-in line driver. The status
of all three FIFOs can be monitored using the external
status pins, or by polling the HI-3582/HI-3583 status
register. Other new features include a programmable
option of data or parity in the 32nd bit, and the ability to
unscramble the 32 bit word. Also, versions are available
with different values of input resistance and output
resistance to allow users to more easily add external
lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-3582/HI-3583 apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
Although the line driver shares a common substrate with
the receivers, the design of the physical isolation does not
allow parasitic crosstalk, and thereby achieves the same
isolation as common hybrid layouts.
HI-3582PQI
HI-3582PQT
&
HI-3583PQI
HI-3583PQT
52
-
51
-
RIN2B
50
-
RIN2A
49
-
RIN1B
48
-
RIN1A
47
-
VDD
46
-
N/C
45
-
TEST
44
-
43
-
TXCLK
42
-
CLK
41
-
40
-
N/C
D/R1
MR
RSR
39 - N/C
38 -
37 - ENTX
36-V+
35 - TXBOUT
34 - TXAOUT
33-V-
32 -
31 -
30 - TX/R
29 -
28 -
27 - BD00
CWSTR
FFT
HFT
PL2
PL1
BD10
-
1
4
BD09
-
1
5
BD08
-1
6
BD07
-1
7
BD06
-1
8
N/C
-1
9
GND
-2
0
N/C
-2
1
BD05
-2
2
BD04
-2
3
BD03
-2
4
BD02
-2
5
BD01
-2
6
FF1
HF1
D/R2
FF2
HF2
EN1
EN2
-1
-2
-3
-4
-5
SEL - 6
-7
-8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
FEATURES
ARINC specification 429 compatible
3.3V logic supply operation
Dual receiver and transmitter interface
Programmable label recognition
32 x 32 FIFOs each receiver and transmitter
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & full military temperature ranges
!
directly to ARINC bus
!
Analog line driver and receivers connect
On-chip 16 label memory for each receiver
Independent data rate selection for
Transmitter and each receiver
APPLICATIONS
!
Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 14 for additional pin configuration)
See Note below
HI-3582PCI
HI-3582PCT
&
HI-3583PCI
HI-3583PCT
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS3582 Rev. D)
12/05
52 - Pin Plastic Quad Flat Pack (PQFP)
December 2005
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