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參數(shù)資料
| 型號： | HGTP5N120CNS9A |
| 英文描述： | TRANSISTOR | IGBT | N-CHAN | 1.2KV V(BR)CES | 25A I(C) | TO-263AB |
| 中文描述： | 晶體管| IGBT的|正陳| 1.2KV五（巴西）國際消費(fèi)電子展|第25A一（c）|至263AB |
| 文件頁數(shù)： | 7/7頁 |
| 文件大?。?/td> | 89K |
| 代理商： | HGTP5N120CNS9A |
7
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to gate-
insulation damage by the electrostatic discharge of energy
through the devices. When handling these devices, care
should be exercised to assure that the static charge built in the
handler’s body capacitance is not discharged through the
device. With proper handling and application procedures,
however, IGBTs are currently being extensively used in
production by numerous equipment manufacturers in military,
industrial and consumer applications, with virtually no
damage problems due to electrostatic discharge. IGBTs can
be handled safely if the following basic precautions are taken:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springsorbytheinsertionintoconductivematerialsuchas
“ECCOSORBD LD26” or equivalent.
2. Whendevicesareremovedbyhandfromtheircarriers,the
hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
5.
Gate Voltage Rating
- Never exceed the gate-voltage
rating of V
GEM
. Exceeding the rated V
GE
can result in
permanent damage to the oxide layer in the gate region.
6.
Gate Termination
- The gates of these devices are
essentially capacitors. Circuits that leave the gate open-
circuited or floating should be avoided. These conditions
canresultinturn-onofthedeviceduetovoltagebuildupon
the input capacitor due to leakage currents or pickup.
7.
Gate Protection
- These devices do not have an internal
monolithic Zener diode from gate to emitter. If gate
protection is required an external Zener is recommended.
Operating Frequency Information
Operating frequency information for a typical device (Figure 3)
is presented as a guide for estimating device performance for
a specific application. Other typical frequency vs collector
current (I
CE
) plots are possible using the information shown
for a typical unit in Figures 5, 6, 7, 8, 9 and 11. The operating
frequency plot (Figure 3) of a typical device shows f
MAX1
or
f
MAX2
; whichever is smaller at each point. The information is
based on measurements of a typical device and is bounded
by the maximum rated junction temperature.
f
MAX1
is defined by f
MAX1
= 0.05/(t
d(OFF)I
+ t
d(ON)I
).
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions are
possible. t
d(OFF)I
and t
d(ON)I
are defined in Figure 19. Device
turn-off delay can establish an additional frequency limiting
condition for an application other than T
JM
. t
d(OFF)I
is
important when controlling output ripple under a lightly loaded
condition.
f
MAX2
is defined by f
MAX2
= (P
D
- P
C
)/(E
OFF
+ E
ON
). The
allowable dissipation (P
D
) is defined by P
D
= (T
JM
- T
C
)/R
θ
JC
.
The sum of device switching and conduction losses must
not exceed P
D
. A 50% duty factor was used (Figure 3) and
the conduction losses (P
C
) are approximated by
P
C
= (V
CE
x I
CE
)/2.
E
ON
and E
OFF
are defined in the switching waveforms shown
in Figure 21. E
ON
is the integral of the instantaneous power
loss (I
CE
x V
CE
) during turn-on and E
OFF
is the integral of the
instantaneous power loss (I
CE
x V
CE
) during turn-off. All tail
losses are included in the calculation for E
OFF
; i.e., the
collector current equals zero (I
CE
= 0).
Test Circuit and Waveforms
FIGURE 20. INDUCTIVE SWITCHING TEST CIRCUIT
FIGURE 21. SWITCHING TEST WAVEFORMS
R
G
= 25
L = 2mH
V
DD
= 960V
+
-
HGTG5N120BND
t
fI
t
d(OFF)I
t
rI
t
d(ON)I
10%
90%
10%
90%
V
CE
I
CE
V
GE
E
OFF
E
ON
HGTG5N120BND, HGTP5N120BND, HGT1S5N120BNDS
ECCOSORBD is a trademark of Emerson and Cumming, Inc.
相關(guān)PDF資料 |
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|---|---|
| HGT1S5N120BNDS | 21A, 1200V, NPT Series N-Channel IGBTs with Anti-Parallel Hyperfast Diodes(21A, 1200V,NPT系列N溝道絕緣柵雙極型晶體管) |
| HGTG5N120BND | 21A, 1200V, NPT Series N-Channel IGBTs with Anti-Parallel Hyperfast Diodes(21A, 1200V,NPT系列N溝道絕緣柵雙極型晶體管) |
| HGTP5N120BND | 21A, 1200V, NPT Series N-Channel IGBTs with Anti-Parallel Hyperfast Diodes(21A, 1200V,NPT系列N溝道絕緣柵雙極型晶體管) |
| HGTP5N120 | 21A, 1200V, NPT Series N-Channel IGBTs with Anti-Parallel Hyperfast Diodes |
| HGTP5N120BND | 3.3V 72-mc CPLD |
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