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參數(shù)資料
| 型號(hào)： | HFCT-6001D |
| 英文描述： | 622 Mb/s Single Mode Fiber Transceiver for ATM, SONET OC-12/SDH STM-4(應(yīng)用于ATM, SONET OC-12/SDH STM-4的622 Mb/s單模式光收發(fā)器) |
| 中文描述： | 622 Mb / s的對(duì)ATM，SONET的OC-12/SDH的STM - 4單模光纖收發(fā)器（應(yīng)用于自動(dòng)取款機(jī)，SONET的OC-12/SDH的STM - 4的622 Mb / s的單模式光收發(fā)器） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 177K |
| 代理商： | HFCT-6001D |
2
Transmitter Section
The transmitter section of the
HFCT-6001 is similar to 1300 nm
single mode transceivers in use at
the 155 Mb/s rate. It consists of a
1300 nm InGaAsP laser in an eye-
safe optical subassembly (OSA)
which mates to the fiber cable.
The laser OSA is driven by a
custom, silicon bipolar IC which
converts differential input PECL
logic signal into an analog laser
drive current.
Receiver Section
transceiver provides a full set of
features including an integral
clock and data recovery (CDR)
circuit together with an optional,
selectable receiver local clock
source.
The receiver utilizes an InGaAs
PIN photodiode mounted
together with a GaAs transimped-
ance preamplifier IC in an OSA.
This OSA is connected to a
custom, silicon bipolar circuit
providing post-amplification and
quantization, CDR function, and
optical signal detection.
Figure 1. Block Diagram
CDR Function
In normal operation, the CDR
data loop is able to acquire and
maintain bit lock without the use
of the optional, external
reference clock. This loop
consists of a patented phase/
frequency detector with false-
lock protection. The recovered
clock is used to re-time the
quantizer data output, which
completes the full CDR function.
The relative timing relationship
between the output re-timed data
and the recovered clock signals
is shown graphically in Figure 2.
For input optical power greater
than the specified receiver
sensitivity of -28 dBm, the bit-
error-ratio will be better than
1 x 10
-10
. As the input power is
decreased by several dB, the bit-
error-ratio degrades. Within 1 dB
below the 1 x 10
-2
BER input
optical power level, the CDR will
begin to lose lock and the clock
frequency will drift from
622.08 MHz. Once the CDR loses
lock, the clock frequency will
sweep through the entire VCO
range, about 540 to 700 MHz. The
rate of the sweep is inversely
proportional to the input optical
power and will reach its
maximum at a point of 2 dB
below the lock point. Since data
is retimed to the clock, a loss of
lock will produce an output data
stream consisting of randomly
switching data bits, i.e. noise.
BAUD INTERVAL
CLOCK PERIOD
RD
RD
CLK
CLK
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
Figure 2. Relative Timing Relationship Between Output Re-timed Data and
Recovered Clock Signals
ELECTRICAL SUBASSEMBLY
RETIMED DATA 2
REFERENCE CLOCK
LOCK-TO-REFERENCE
SIGNAL DETECT
CLOCK & DATA
RECOVERY
AND POST
AMPLIFIER IC
LASER
DRIVER
IC
PRE-
AMPLIFIER
IC
LASER
PIN PHOTODIODE
DUPLEX SC
RECEPTACLE
TOP VIEW
OPTICAL
SUB-
ASSEMBLIES
RECOVERED CLOCK 2
DATA 2
LASER BIAS MONITOR
POWER
MONITOR
TRANSMIT
DISABLE
RECEIVE POWER MONITOR
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