參數(shù)資料
型號: HFBR-1116T
英文描述: Fiber Optic Transmitter Data Links for 155 MBd(應(yīng)用于155 MBd的光纖傳送數(shù)據(jù)鏈路)
中文描述: 光纖發(fā)射數(shù)據(jù)鏈接為155 MBd的(應(yīng)用于155 MBd的的光纖傳送數(shù)據(jù)鏈路)
文件頁數(shù): 5/12頁
文件大小: 212K
代理商: HFBR-1116T
5
NC 8
9 NC
GND 7
10
V
CC
6
11 GND
V
CC
5
12 GND
V
CC
4
13 GND
D 3
14 SD
D
2
15 SD
NC 1
16
Rx
A
*
L1
1
R12
130
DATA
DATA
TERMINATE D, D, SD, SD AT
INPUTS OF FOLLOW-ON DEVICES
*
NO
NO
C1
0.1
C7
10
(OPTIONAL)
C3
0.1
C4
10
R6
130
R8
130
R5
82
R7
82
R9
82
C6
0.1
SD
R11
82
SD
R10
130
TOP VIEWS
NC 8
NO
9 NC
7
10 GND
GND 6
11 V
CC
GND 5
12 V
CC
GND 4
13 GND
GND 3
14 D
V
BB
2
15 D
NC 1
16 NC
Tx
A
C2
0.1
*
L2
1
R3
82
R4
130
R2
82
R1
130
C5
0.1
+5 Vdc
GND
DATA
DATA
TERMINATE D, D
AT Tx INPUTS
*
Shipping Container
The data link modules are
packaged in a shipping container
designed to protect it from
mechanical and ESD damage
during shipment or storage.
Board Layout–Interface
Circuit and Layout
Guidelines
It is important to take care in the
layout of your circuit board to
achieve optimum performance
from these data link modules.
Figure 7 provides a good example
of a power supply filter circuit that
works well with these parts. Also,
suggested signal terminations for
the Data, Data-bar, Signal Detect
and Signal Detect-bar lines are
shown. Use of a multilayer,
ground-plane printed circuit board
will provide good high-frequency
circuit performance with a low
inductance ground return path. See
additional recommendations noted
in the interface schematic shown in
Figure 7.
Figure 7. Recommended Interface Circuitry and Power Supply Filter Circuits.
NOTES:
1. RESISTANCE IS IN OHMS. CAPACITANCE IS IN MICROFARADS. INDUCTANCE IS IN MICROHENRIES.
2. TERMINATE TRANSMITTER INPUT DATA AND DATA-BAR AT THE TRANSMITTER INPUT PINS. TERMINATE THE RECEIVER OUTPUT DATA, DATA-BAR, AND SIGNAL DETECT-
BAR AT THE FOLLOW-ON DEVICE INPUT PINS. FOR LOWER POWER DISSIPATION IN THE SIGNAL DETECT TERMINATION CIRCUITRY WITH SMALL COMPROMISE TO THE
SIGNAL QUALITY, EACH SIGNAL DETECT OUTPUT CAN BE LOADED WITH 510 OHMS TO GROUND INSTEAD OF THE TWO RESISTOR, SPLIT-LOAD PECL TERMINATION
SHOWN IN THIS SCHEMATIC.
3. MAKE DIFFERENTIAL SIGNAL PATHS SHORT AND OF SAME LENGTH WITH EQUAL TERMINATION IMPEDANCE.
4. SIGNAL TRACES SHOULD BE 50 OHMS MICROSTRIP OR STRIPLINE TRANSMISSION LINES. USE MULTILAYER, GROUND-PLANE PRINTED CIRCUIT BOARD FOR BEST HIGH-
FREQUENCY PERFORMANCE.
5. USE HIGH-FREQUENCY, MONOLITHIC CERAMIC BYPASS CAPACITORS AND LOW SERIES DC RESISTANCE INDUCTORS. RECOMMEND USE OF SURFACE-MOUNT COIL
INDUCTORS AND CAPACITORS. IN LOW NOISE POWER SUPPLY SYSTEMS, FERRITE BEAD INDUCTORS CAN BE SUBSTITUTED FOR COIL INDUCTORS. LOCATE POWER
SUPPLY FILTER COMPONENTS CLOSE TO THEIR RESPECTIVE POWER SUPPLY PINS. C7 IS AN OPTIONAL BYPASS CAPACITOR FOR IMPROVED, LOW-FREQUENCY NOISE
POWER SUPPLY FILTER PERFORMANCE.
6. DEVICE GROUND PINS SHOULD BE DIRECTLY AND INDIVIDUALLY CONNECTED TO GROUND.
7. CAUTION: DO NOT DIRECTLY CONNECT THE FIBER-OPTIC MODULE PECL OUTPUTS (DATA, DATA-BAR, SIGNAL DETECT, SIGNAL DETECT-BAR, V
BB
) TO GROUND WITHOUT
PROPER CURRENT LIMITING IMPEDANCE.
8. (*) OPTIONAL METAL ST OPTICAL PORT TRANSMITTER AND RECEIVER MODULES WILL HAVE PINS 8 AND 9 ELECTRICALLY CONNECTED TO THE METAL PORT ONLY AND
NOT CONNECTED TO THE INTERNAL SIGNAL GROUND.
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