參數(shù)資料
型號(hào)： HFA3863IN96
廠商： INTERSIL CORP
元件分類： 無(wú)繩電話/電話
英文描述： Direct Sequence Spread Spectrum Baseband Processor
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64
封裝： 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64
文件頁(yè)數(shù)： 25/39頁(yè)
文件大?。?/td> 305K
代理商： HFA3863IN96
4-25
CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD
Bits 7:5
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 4
TX/RX filter / CMF weight select.
0 = US.
1 = Japan.
Bits 3
Select preamble mode.
0 = Normal, long preamble interoperable with 1 and 2Mbps legacy equipment.
1 = short preamble and header mode (optional in 802.11).
Bit 2
Reserved, must be set to 0.
Bits 1:0
TX data Rate. Must be set at least 2
μ
s before needed in TX frame. This selects TX signal field code from the registers above.
00 = DBPSK - 11 chip sequence (1Mbps).
01 = DQPSK - 11 chip sequence (2Mbps).
10 = CCK - 8 chip sequence (5.5Mbps).
11 = CCK - 8 chip sequence (11Mbps).
CONFIGURATION REGISTER 6 ADDRESS (0Ch) R/W TX SERVICE FIELD
Bits 7:0
Bit 7 may be employed by the MAC in 802.11 situations to resolve an ambiguity in the length field when in the 11Mbps mode.
Bit 2 should be set to a 1 where the reference oscillator of the radio is common for both the carrier frequency and the data
clock. All other bits should be set to 0 to ensure compatibility.
CONFIGURATION REGISTER 7 ADDRESS (0Eh) R/W TX LENGTH FIELD (HIGH)
Bits 7:0
This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte combined
with the lower byte indicates the number of microseconds the data packet will take.
CONFIGURATION REGISTER 8 ADDRESS (10h) R/W TX LENGTH FIELD (LOW)
Bits 7:0
This 8-bit register contains the lower byte (bits 0-7) of the transmit Length Field described in the Header. This byte combined
with the higher byte indicates the number of microseconds the data packet will take.
CONFIGURATION REGISTER 9 ADDRESS (12h) R/W TX CONFIGURE
Bit 7
CCA sample mode time.
0 = 18.7
μ
s.
1 = 15.8
μ
s.
Bits 6:5
CCA mode.
00 - CCA is based only on ED.
01 - CCA is based on (CS1 OR SQ1).
10 - CCA is based on (ED AND (CS1 OR SQ1)).
11 - CCA is based on (ED OR (CS1 OR SQ1)).
Bit 4
TX test modes.
0 = Alternating bits for carrier suppression test. (Needs scrambler off (CR32 [2] = 1)).
1 = all chips set to 1 for CW carrier. This allows frequency measurement.
Bit 3
Enable TX test modes.
0 = normal operation.
1 = Invoke tests described by bit 4.
Bit 2
Antenna choice for TX when TX antenna diversity is disabled.
0 = Set AntSel low.
1 = Set AntSel high.
Bit 1
TX Antenna Mode.
0 = Disable diversity, set AntSel pin to value in bit 2.
1 = Enable diversity, set AntSel pin to antenna for which last valid received header CRC occurred.
Bit 0
High Rate cover code disable.
0 = Enable.
1 = Disable.
HFA3863
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