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參數(shù)資料
| 型號(hào)： | HFA3861B |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)譜基帶處理器） |
| 文件頁數(shù)： | 31/37頁 |
| 文件大小： | 284K |
| 代理商： | HFA3861B |
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31
CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE LEAD COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Preamble Lead Coefficient (0-4 range) (000000 - 100000)
CONFIGURATION REGISTER ADDRESS 42 (54h) R/W PREAMBLE LAG COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Preamble Lag Coefficient (0-4 range) (000000 - 100000)
CONFIGURATION REGISTER ADDRESS 43 (56h) R/W HEADER LEAD COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Header Lead Coefficient (0-4 range) (000000 - 100000)
CONFIGURATION REGISTER ADDRESS 44 (58h) R/W HEADER LAG COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Header Lag Coefficient (0-4 range) (000000 - 100000)
CONFIGURATION REGISTER ADDRESS 45 (5Ah) R/W DATA LEAD COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Data Lead Coefficient (0-4 range) (000000 - 100000)
CONFIGURATION REGISTER ADDRESS 46 (5Ch) R/W DATA LAG COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Data Lag Coefficient (0-4 range) (000000 - 100000)
CONFIGURATION REGISTER ADDRESS 47 (5Eh) R/W RF ATTENUATOR VALUE
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
CR_AGC_rxAGCpad value to use in the RSSI calculation. Range 0-63.
CONFIGURATION REGISTER ADDRESS 48 (60h) R/W ACQUISITION CONTROL
Bit 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6
ED and SQ1 control for acquisition
0 = SQ1
1 = ED and SQ1
Bits 5:0
SQ1 scale factor (0-7.875 range) (000.000-111.111)
CONFIGURATION REGISTER ADDRESS 49 (62h) R/W READ ONLY REGISTER MUX CONTROL
Bit 7
Read only register mux control
0 = READ ONLY registers read ‘b’ value
1 = READ ONLY registers read ‘a(chǎn)’ value
Bits 6:0
CW RSSI threshold.
When CW is present and RSSI< threshold, use default CMF weights.
When CW is present and RSSI> threshold, use calculated CMF weights.
To force default or calculated weights, see CR35
CONFIGURATION REGISTER ADDRESS 50 (64h) R TEST BUS READ
Bit 7:0
a&b: reads value on test bus
CONFIGURATION REGISTER ADDRESS 51 (66h) R SIGNAL QUALITY MEASURE
Bit 7:0
a: NOISEfloorAntA [7:0] unsigned, range 0-255
b: measures signal quality based on the SNR in the carrier tracking loop
CONFIGURATION REGISTER ADDRESS 52 (68h) R RECEIVED SIGNAL FIELD
Bit 7:0
a: NOISEfloorAntB [7:0] unsigned, range 0-255
b: 8-bit value of received signal field
HFA3861B
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PDF描述 |
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| HFA3861 | Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴(kuò)頻基帶處理器) |
| HFA3861IV | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 2.4GHz - 2.5GHz 250mW Power Amplifier(2.4GHz - 2.5GHz 250mW 功率放大器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861BIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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