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參數(shù)資料
| 型號： | HFA3861AIN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 288 MACROCELL 3.3 VOLT ISP CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, MS-026ACD, TQFP-64 |
| 文件頁數(shù)： | 3/37頁 |
| 文件大?。?/td> | 440K |
| 代理商： | HFA3861AIN |
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3
Pin Descriptions
NAME
PIN
TYPE I/O
DESCRIPTION
V
DDA
(Analog)
12, 17, 22,
31
Power
DC power supply 2.7V - 3.6V (Not Hard wired Together On Chip).
V
DDD
(Digital)
GNDa
(Analog)
2, 8, 37, 57
Power
DC power supply 2.7 - 3.6V.
9, 15, 20,
25, 28,
Ground
DC power supply 2.7 - 3.6V, ground (Not Hard wired Together On Chip).
GNDd (Digital) 1, 7, 36, 43,
56
Ground
DC power supply 2.7 - 3.6V, ground.
V
REF
I
REF
RXI
, +/-
RXQ
, +/-
ANTSEL
16
I
Voltage reference for A/D’s and D/A’s.
21
I
Current reference for internal ADC and DAC devices. Requires a 12k
resistor to ground.
10/11
I
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-.
13/14
I
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-.
39
O
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for
differential drive of antenna switches.
ANTSEL
40
O
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for
differential drive of antenna switches.
RX_IF_DET
19
I
Analog input to the receive power A/D converter for AGC control.
RX_IF_AGC
34
O
Analog drive to the IF AGC control.
RX_RF_AGC
38
O
Drive to the RF AGC stage attenuator. CMOS digital.
TX_AGC_IN
18
I
Input to the transmit power A/D converter for transmit AGC control.
TX_IF_AGC
35
O
Analog drive to the transmit IF power control.
TX_PE
62
I
When active, the transmitter is configured to be operational, otherwise the transmitter is in standby
mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to
the HFA3861A. The rising edge of TX_PE will start the internal transmit state machine and the falling
edge will initiate shut down of the state machine. TX_PE envelopes the transmit data except for the
last bit. The transmitter will continue to run for 4
μ
s after TX_PE goes inactive to allow the PA to shut
down gracefully.
TXD
58
I
TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network
processor to the HFA3861A. The data is received serially with the LSB first. The data is clocked in the
HFA3861A at the rising edge of TXCLK.
TXCLK
55
O
TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to
the HFA3861A, synchronously. Transmit data on the TXD bus is clocked into the HFA3861A on the
rising edge. The clocking edge is also programmable to be on either phase of the clock. The rate of
the clock will be dependent upon the data rate that is programmed in the signalling field of the header.
TX_RDY
59
O
TX_RDY is an output to the external network processor indicating that Preamble and Header
information has been generated and that the HFA3861A is ready to receive the data packet from the
network processor over the TXD serial bus.
CCA
60
O
Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The
CCA may be configured to one of four possible algorithms. The CCA algorithm and its features are
described elsewhere in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
This polarity is programmable and can be inverted.
RXD
53
O
RXD is an output to the external network processor transferring demodulated Header information and
data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with
MD_RDY.
RXCLK
52
O
RXCLK is the bit clock output. This clock is used to transfer Header information and payload data
through the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is
held to a logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been
detected. Data should be sampled on the rising edge. This polarity is programmable and can be
inverted.
HFA3861A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA3863IN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863 | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
| HFA3983IV96 | 2.4GHz Power Amplifier and Detector |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861AIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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