參數(shù)資料
型號(hào)： HFA3860AIV
廠商： INTERSIL CORP
元件分類： 無(wú)繩電話/電話
英文描述： 3.3V 288-mc CPLD
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
封裝： 7 X 7 X 1 MM, PLASTIC, TQFP-48
文件頁(yè)數(shù)： 31/39頁(yè)
文件大?。?/td> 251K
代理商： HFA3860AIV
2-161
CONFIGURATION REGISTER 26 ADDRESS (68h) RX LENGTH FIELD STATUS (HIGH)
Bits 7:0
This register contains the detected higher byte (bits 8-15) of the received Length Field contained in the Header. This byte
combined with the lower byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER ADDRESS 27 (6Ch) RX LENGTH FIELD STATUS (LOW)
Bits 7:0
This register contains the detected lower byte of the received Length Field contained in the Header. This byte combined with
the upper byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS
Supplies address for test pin outputs and Test Bus Monitor Register
Bits 7:0
Test Bus Address = 00h
Quiet Test Bus
Test 7:0 = 00
TEST_CLK = 0
Bits 7:0
Test Bus Address = 01h
RX Acquisition Monitor
These bits sequentially go high as the signal is input. Transitions are aligned to chip boundaries.
Bits are reset after last chip of message.
Test 7 = A/DCal (Full Scale)
Test 6 = CRS, Carrier Sense
Test 5 = ED, energy detect comparator output
Test 4 = Track, indicates start of tracking and start of SFD time-out
Test 3 = SFD Detect, variable time after track start
Test 2 = Signal Field Ready, ~ 8
μ
s after SFD Detect
Test 1 = Length Field Ready, ~ 32
μ
s after SFD Detect
Test 0 = Header CRC Valid, ~ 48
μ
s after SFD Detect
TEST_CLK = Initial Detect
Bits 7:0
Test Bus Address = 02h
TX Field Monitor.
These bits sequentially go high as the signal is output. Transitions are aligned to chip boundaries. Bits
are reset after last chip of valid message.
Test 7 = A/DCal (Full Scale)
Test 6 = TXPE Internal, Inactive edge of pad TXPE delayed
Test 5 = Preamble Start
Test 4 = SFD Start
Test 3 = Signal Field Start
Test 2 = Length Field Start
Test 1 = Header CRC Start
Test 0 = MPDU Start
TEST_CLK = IQMARK, identifies symbol boundaries on IOUT and QOUT
Bits 7:0
Test Bus Address = 03h
RSSI Monitor
Test 7 = CSE Enhanced. Used in enhanced CCA dual antenna mode.
Test 6 = CSE, Carrier Sense Early (SQI CCA Only)
Test 5:0 = RSSI(5:), bit 5 is MSB, straight binary (000000 = Min, 11111 = Max)
TEST_CLK = RSSI A/D CLK, Sample RSSI(5:0) on last rising edge
Bits 7:0
Test Bus Address = 04h
SQ1 Monitor
Test 7:0 = SQ1 (7:0)
TEST_CLK = pulse after SQ is valid
Bits 7:0
Test Bus Address = 05h
SQ2 Monitor
- SQ3 output if SQ3 used for antenna diversity.
Test 7:0 = SQ2 (7:0)
TEST_CLK = pulse after SQ is valid
Bits 7:0
Test Bus Address = 06h
Correlator Lo Rate
Test 7:0 = Correlator Magnitude Lo Rate Only
TEST_CLK = Sample CLK
HFA3860A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HFA3860AIV WAF 制造商:Harris Corporation 功能描述:
HFA3860AIV96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband
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HFA3860BIV WAF 制造商:Harris Corporation 功能描述:
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