參數(shù)資料
型號： HFA3842
廠商： Intersil Corporation
英文描述： Wireless LAN Medium Access Controller
中文描述： 無線局域網(wǎng)媒體訪問控制器
文件頁數(shù)： 7/26頁
文件大?。?/td> 512K
代理商： HFA3842
7
SYSTEM INTERFACE - PC CARD IO READ 16
Data Delay After HIORD-
Data Hold Following HIORD-
HIORD- Width Time
Address Setup Before HIORD-
Address Hold Following HIORD-
HCE(1, 2)- Setup Before HIORD-
HCE(1, 2)- Hold After HIORD-
HREG- Setup Before HIORD-
HREG- Hold Following HIORD-
HINPACK- Delay Falling from HIORD-
HINPACK- Delay Rising from HIORD-
Data Delay from HWAIT- Rising
HWAIT- Width Time
SYSTEM INTERFACE - PC CARD IO WRITE 16
Data Setup Before HIORD-
Data Hold Following HIORD-
HIOWR- Width Time
Address Setup Before HIORD-
Address Hold Following HIORD-
HCE(1, 2)- Setup Before HIORD-
HCE(1, 2)- Hold Following HIORD-
HREG- Setup Before HIORD-
HREG- Hold Following HIORD-
HWAIT- Delay Falling from HIORD-
HWAIT- Width Time
HIOWR- High from HWAIT- High
RADIO TX DATA - TX PATH
TXC Period
TXC Width Hi
TXC Width Lo
RADIO RX DATA - RX PATH
RX_RDY Setup Time to RXC Positive Edge (See Note 5)
RX_RDY Hold Time from RXC Positive Edge (See Note 6)
RX_PE2 Delay from RX_RDY deAssert (See Note 10)
RX_PE2 Low Pulse Width (See Note 9)
RXD Setup Time to RXC Positive Edge (See Note 7)
RXD Hold Time from RXC Positive Edge (See Note 7)
RXC Period (See Note 12)
RXC Width Hi
RXC Width Lo
NOTES:
6. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. RX_RDY is not required to be valid until 1 MCLK after RXC is
sampled high. Therefore, a negative setup time could be used. Since this is an unlikely scenario, we will leave it at a nominal 10ns setup time.
7. MD_RDY is and'ed with RXC_ONE_SHOT (RXDAV) to shift data in shift register. Therefore, for the last data bit, the MD_RDY must be held
active until RXC_ONE_SHOT is sampled high by MAC's MCLK. However, it is assumed that BBP will be used in a mode that keeps RX_RDY
(MD_RDY) and RXC running until RX_PE2 is de-asserted. The MAC will stop processing data after the number of bits retrieved from the PLCP
header length field are received. Therefore, the RX_RDY hold time with respect to RXC does not matter. However, should the RX_RDY signal
be cleared when the last RXD bit is received the hold time w/r RXC must be honored.
8. RXC positive edge clocks a flop which stores the RXD for internal usage.
9. RXC period (and Hi/Lo times) must be long enough for flops clocked by MAC MCLK to see 1 RXC high and 1 RXC low.
10. RX_PE inactive width at BBP is 3 BBP CLK's. Since BBP CLK and MAC CLK can be async minimum should be 4 MAC CLKs.
11. When RX_RDY drops before expected number of RXD bits is received, then TX/RX FSM in mpctl.v signals timers which clear rx_pe2_int.
t
DIORD
t
HIORD
t
WIORD
t
SUA
t
HA
t
SUCE
t
HCE
t
SUREG
t
HREG
t
DFINPACK
d
DRINPACK
t
DRWT
t
WWT
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
100
-
-
-
-
-
-
-
-
45
45
0
12,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
165
70
20
5
20
5
0
0
30
-
-
t
SUIOWR
t
HIOWR
t
WIOWR
t
SUA
t
HA
t
SUCE
t
HCE
t
SUREG
t
HREG
t
DFWT
t
WWT
t
DRIOWR
30
20
165
70
20
5
20
5
0
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
92
-
-
-
-
-
-
-
-
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12,000
-
t
TXC
t
CHM
t
CLM
4* t
TMCK
31
31
-
-
-
-
-
-
ns
ns
ns
t
SURX_RDY
t
HRX_RDY
t
DRX_PE2
t
WRX_PE2
t
SURXD
t
HRXD
t
RXC
t
RCHM
t
RCLM
10
45
-
-
10
0
-
31
31
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
3 * t
MCLK
4 * t
MCLK
-
-
3 * t
MCLK
-
-
AC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
HFA3842
相關(guān)PDF資料
PDF描述
HFA3842IN Wireless LAN Medium Access Controller
HFA3860AIV96 Circular Connector; No. of Contacts:5; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-5 RoHS Compliant: No
HFA3860A Direct Sequence Spread Spectrum Baseband
HFA3860AIV 3.3V 288-mc CPLD
HFA3861AIN96 Circular Connector; No. of Contacts:21; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-21 RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HFA3842A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller
HFA3842AIN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller
HFA3842AIN-TK 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller
HFA3842B 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller
HFA3842BIN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller
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