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參數(shù)資料
| 型號： | HFA3783 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 衰減器 |
| 英文描述： | 288 MACROCELL 3.3 VOLT ISP CPLD |
| 中文描述： | 70 MHz - 600 MHz RF/MICROWAVE I/Q MODEM |
| 文件頁數(shù)： | 10/34頁 |
| 文件大?。?/td> | 608K |
| 代理商： | HFA3783 |
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10
Phase Lock Loop Electrical Specifications
PARAMETER
TEST CONDITIONS
TEMP.
(
o
C)
MIN
TYP
MAX
UNITS
Operating 2X LO Frequency
Test Diagram
Full
140
-
1200
MHz
Reference Oscillator Frequency
Test Diagram
Full
-
-
50
MHz
Selectable Prescaler Ratios (2 Settings)
Full
16/17
N/A
32/33
-
Swallow Counter Divide Ratio (A Counter)
Full
0
-
127
-
Programmable Counter Divide Ratio
(B Counter)
Full
3
-
2047
-
Reference Counter Divide Ratio (R Counter)
Full
3
-
32767
-
Reference Oscillator Sensitivity
Single or Differential Sine
Inputs
Full
0.5
-
-
V
PP
CMOS Single or
Complementary
Full
-
CMOS
-
-
Reference Oscillator Duty Cycle
CMOS Inputs
Full
40
-
60
%
Charge Pump Sink/Source Current/Tolerance
250
μ
A Selection +/- 25%
Full
0.18
0.25
0.32
mA
Charge Pump Sink/Source Current/Tolerance
500
μ
A Selection +/- 25%
Full
0.375
0.5
0.625
mA
Charge Pump Sink/Source Current/Tolerance
750
μ
A Selection +/- 25%
Full
0.56
0.75
0.94
mA
Charge Pump Sink/Source Current/Tolerance
1mA Selection +/- 25%
Full
0.75
1.0
1.25
mA
Charge Pump Sink/Source Mismatch
Full
-
-
15
%
Charge Pump Output Compliance
Full
0.5
-
CPV
DD
-
0.5
V
Charge Pump High Z leakage
High Z state
Full
-10
±
0.1
10
μ
A
Charge Pump Supply Voltage
Full
2.7
-
3.6
V
Serial Interface Clock Width
High Level
Full
20
-
-
ns
Low level
Full
20
-
-
ns
Serial Interface Data/Clk Set-Up Time
Full
20
-
-
ns
Serial Interface Data/Clk Hold Time
Full
10
-
-
ns
Serial Interface Clk/LE Set-Up Time
Full
20
-
-
ns
Serial Interface LE Pulse Width
Full
20
-
-
ns
POWER ENABLE TRUTH TABLE
PE1
PE2
PLL_PE
(SERIAL BUS)
STATUS
0
0
1
Power Down State, PLL Registers in Save Mode, Inactive PLL, Active Serial Interface
1
1
1
Receive State, Active PLL
1
0
1
Transmit State, Active PLL
0
1
1
Inactive Transmit and Receive States, Active PLL, Active Serial Interface
X
X
0
Inactive PLL, Disabled PLL Registers, Active Serial Interface
PLL Synthesizer and DC Offset Clock Programming Table
SERIAL
BITS
REGISTER
DEFINITION
LSB 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MSB
R Counter
0
0
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14)
X (Don’t Care)
A/B Counter
0
1
A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
B(10)
HFA3783
相關PDF資料 |
PDF描述 |
|---|---|
| HFA3783IN | I/Q Modulator/Demodulator and Synthesizer |
| HFA3824AIV96 | JT 5C 5#20 PIN WALL RECP |
| HFA3824AIV | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3824A | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3842B | PCMCIA/USB Wireless LAN Medium Access Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3783IN | 制造商:Intersil Corporation 功能描述: |
| HFA3783IN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:I/Q Modulator/Demodulator and Synthesizer |
| HFA3824 WAF | 制造商:Harris Corporation 功能描述: |
| HFA3824A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3824AIV | 制造商:Rochester Electronics LLC 功能描述:BASEBAND PROCESSOR - Bulk |
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