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參數(shù)資料
| 型號： | HFA1412IBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 0K |
| 描述： | IC BUFFER QUAD 350MHZ LP 14-SOIC |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | 緩沖器 |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 1700 V/µs |
| -3db帶寬： | 350MHz |
| 電流 - 輸入偏壓： | 1µA |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 5.9mA |
| 電流 - 輸出 / 通道： | 55mA |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 11 V，±4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1234 (CN2011-ZH PDF) |
6
FN4152.4
January 23, 2006
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB). The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10
F) tantalum in parallel with a small value
(0.1
F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
350MHz. By decreasing RS as CL increases (as illustrated in
the curves), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth decreases as
the load capacitance increases. For example, at AV =+2,
RS =22, CL = 100pF, the overall bandwidth is 125MHz, and
bandwidth drops to 100MHz at RS =12, CL = 220pF.
Evaluation Board
The performance of the HFA1412 may be evaluated using
the HA5025 Evaluation Board, slightly modified as follows:
1. Remove the four feedback resistors, and leave the
connections open.
2. a. For AV = +1 evaluation, remove the gain setting
resistors (R1), and leave pins 2, 6, 9, and 13 floating.
b. For AV = +2, replace the gain setting resistors (R1) with
0
resistors to GND.
3. Replace the 0
series output resistors with 50.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
To order evaluation boards (part number HA5025EVAL),
please contact your local sales office.
0
100
200
300
400
0
10
20
30
40
50
LOAD CAPACITANCE (pF)
SERI
ES
OUTP
U
T
RESI
ST
AN
CE
(
)
AV =+1
AV =+2
150
250
350
50
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
+5V
10
F0.1F
50
GND
R1
-5V
0.1
F
10
F
50
IN
OUT
∞ (AV = +1)
or 0
(A
V = +2)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NOTE: R1 =
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
+
-
(NOTE)
FIGURE 3A. TOP LAYOUT
FIGURE 3B. BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
HFA1412
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