參數(shù)資料
型號: HFA1130883
廠商: Intersil Corporation
英文描述: Output Clamping, 850MHz Current Feedback Amplifier
中文描述: 輸出鉗位,850MHz的電流反饋放大器
文件頁數(shù): 16/19頁
文件大?。?/td> 865K
代理商: HFA1130883
DESIGN INFORMATION
(Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
219
HFA1130
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
Clamp Operation
General
The HFA1130 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the V
H
and V
L
terminals (DIP pins 8
and 5) of the amplifier. V
H
sets the upper output limit, while
V
L
sets the lower clamp level. If the amplifier tries to drive
the output above V
H
, or below V
L
, the clamp circuitry limits
the output voltage at V
H
or V
L
(
±
the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
V
H
+IN
V
L
V+
GND
1
V-
OUT
TOP LAYOUT
BOTTOM LAYOUT
1
2
3
4
8
7
6
5
+5V
10
μ
F
0.1
μ
F
V
H
50
GND
GND
R1
-5V
0.1
μ
F
10
μ
F
50
IN
OUT
V
L
500
500
FIGURE 3. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY
Clamp Circuitry
Figure 3 shows a simplified schematic of the HFA1130 input
stage, and the high clamp (V
H
) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
(V
-IN
- V
OUT
)/R
F
+ V
-IN
/ R
G
where R
G
is the gain setting resistor from -IN to GND. This
current is mirrored onto the high impedance node (Z) by
QX3 - QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches it’s qui-
escent value, the current flowing through -IN is reduced to
only that small current (-I
BIAS
) required to keep the output at
the final voltage.
Tracing the path from V
H
to Z illustrates the effect of the
clamp voltage on the high impedance node. V
H
decreases
by 2V
BE
(QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2V
BE
(QP5
and QN5). Thus, QP5 clamps node Z whenever Z reaches
V
H
. R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by V
L
.
+1
+IN
V-
V+
QP1
QN1
V-
QN3
QP3
QP4
QN2
QP2
QN4QP5
QN5
Z
V+
-IN
V
OUT
I
CLAMP
R
F
(EXTERNAL)
QP6
QN6
V
H
R1
50K
(30K
FOR V
L
)
Spec Number
511082-883
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