250
8.8.2
Register Configuration
Table 8.13 shows the port C register configuration.
Table 8.13
Port C Registers
Name
Abbreviation
R/W
Initial Value
Address
*
Port C data direction register
PCDDR
W
H'00
H'FEBB
Port C data register
PCDR
R/W
H'00
H'FF6B
Port C register
PORTC
R
Undefined
H'FF5B
Port C MOS pull-up control register
Note:
*
Lower 16 bits of the address.
PCPCR
R/W
H'00
H'FF72
Port C Data Direction Register (PCDDR)
7
PC7DDR
0
W
6
PC6DDR
0
W
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
0
PC0DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
Bit
Initial value
R/W
:
:
:
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to
select whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
Modes 1, 4, and 5*
The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.
Modes 2 and 6*
Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while
clearing the bit to 0 makes the pin an input port.
Modes 3 and 7*
Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing
the bit to 0 makes the pin an input port.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.