參數(shù)資料
型號: HEF4024BT
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 7-stage binary counter
封裝: HEF4024BP<SOT27-1 (DIP14)|<<http://www.nxp.com/packages/SOT27-1.html<1<Always Pb-free,;HEF4024BT<SOT108-1 (SO14)|<<http://www.nxp.com/packages/SOT108-1.html<1<week
文件頁數(shù): 1/14頁
文件大?。?/td> 100K
代理商: HEF4024BT
1. General description
The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a
static toggle flip-flop.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input. It is
also suitable for use over the full industrial (
40
C to +85
C) temperature range.
2. Features and benefits
Tolerant of slow clock rise and fall time
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range
40
C to +85
C
Complies with JEDEC standard JESD 13-B
3. Applications
Frequency dividers
Time delay circuits
4. Ordering information
HEF4024B
7-stage binary counter
Rev. 6 — 10 October 2011
Product data sheet
Table 1.
All types operate from
40
C to +125
C
Type number
Ordering information
Package
Name
DIP14
SO14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads; body width 3.9 mm
Version
SOT27-1
SOT108-1
HEF4024BP
HEF4024BT
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