參數(shù)資料
型號: HEF4013BT,652
廠商: NXP Semiconductors
文件頁數(shù): 1/16頁
文件大?。?/td> 0K
描述: IC FLIP FLOP DUAL D TYPE 14SOIC
產(chǎn)品培訓模塊: Logic Packages
標準包裝: 57
系列: 4000B
功能: 設置(預設)和復位
類型: D 型
輸出類型: 差分
元件數(shù): 2
每個元件的位元數(shù): 1
頻率 - 時鐘: 40MHz
延遲時間 - 傳輸: 30ns
觸發(fā)器類型: 正邊沿
輸出電流高,低: 3.4mA,3.4mA
電源電壓: 3 V ~ 15 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 842 (CN2011-ZH PDF)
其它名稱: 568-1685-5
933372660652
HEF4013BTD
1.
General description
The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD),
clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is
LOW and is transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous CD and SD inputs are independent and override the D or CP inputs.
The outputs are buffered for best system performance. The clock input’s Schmitt-trigger
action makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2.
Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C to +125 C
Complies with JEDEC standard JESD 13-B
3.
Applications
Counters and dividers
Registers
Toggle flip-flops
4.
Ordering information
HEF4013B
Dual D-type flip-flop
Rev. 8 — 21 November 2011
Product data sheet
Table 1.
Ordering information
All types operate from
40 C to +125 C
Type number
Package
Name
Description
Version
HEF4013BP
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
HEF4013BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
HEF4013BTT
TSSOP14
plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
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