參數(shù)資料
型號(hào): HEC4040BT,112
廠商: NXP Semiconductors
文件頁(yè)數(shù): 11/14頁(yè)
文件大小: 0K
描述: IC 12STAGE BINARY COUNTER 16SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 50
系列: 4000B
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向:
元件數(shù): 1
每個(gè)元件的位元數(shù): 12
復(fù)位: 異步
觸發(fā)器類型: 負(fù)邊沿
電源電壓: 4.5 V ~ 15.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 管件
其它名稱: 935249730112
HEC4040BT
HEC4040BT-ND
HEF4040B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 17 November 2011
6 of 14
NXP Semiconductors
HEF4040B
12-stage binary ripple counter
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2]
For loads other than 50 pF at the nth output, use the slope given.
[3]
tt is the same as tTHL and tTLH.
tt
transition time
5 V
[3] 10 ns + (1.00 ns/pF)CL
-
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
-30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
-20
40
ns
tW
pulse width
CP input HIGH;
minimum width;
5 V
5025-
ns
10 V
3015-
ns
15 V
2010-
ns
MR input HIGH;
minimum width;
5 V
4020-
ns
10 V
3015-
ns
15 V
2010-
ns
trec
recovery time
MR input;
5 V
4020-
ns
10 V
3015-
ns
15 V
2010-
ns
fmax
maximum
frequency
CP input;
5 V
1020-
MHz
10 V
1530-
MHz
15 V
2550-
MHz
Table 6.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; unless otherwise specified; for test circuit see Figure 6.
Symbol
Parameter
Conditions
VDD
Extrapolation formula[1]
Min
Typ
Max
Unit
Table 7.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power
dissipation
5 V
PD = 400 fi + (fo CL) VDD2
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(f
o CL) = sum of the outputs.
10 V
PD = 2000 fi + (fo CL) VDD2
15 V
PD = 5200 fi + (fo CL) VDD2
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