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參數資料
| 型號： | HE84G770(S) |
| 文件頁數： | 44/52頁 |
| 文件大?。?/td> | 631K |
| 代理商： | HE84G770(S) |
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20.5.
Line Status Register
KING BILLION ELECTRONICS CO., LTD
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億
電
子
股
份
有
限
公
司
HE84G761
HE80004 Series
June 30, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
44
V1.01
Bit 7
0
Bit 6
TEMT
Bit 5
THRE
Bit 4
BI
Bit 3
FE
Bit 2
PE
Bit 1
OE
Bit 0
DR
Name
Description
DR
Receiver Data Ready
DR indicates status of RBR. It will be set to logic 1 when RBR data is valid and will
be reset to logic 0 when RBR is empty. When line errors (OE/PE/FE/BI) happen, DR
will also be set to logic 1 and RBR will be updated to reflect the Data bits portion of
the frame.
Overrun Error
This bit will be set when the next character is transferred into RBR before the
previous RBR data is read by the CPU. Even though DR will still be 1 when OE is set
to logic 1, the previous frame data stored in RBR which is not read by the CPU is
trashed and can‘t be recovered.
Parity Error
This bit will be set to logic 1 only when the Parity is enabled and the Parity bit is not
at the logic state it should be. For Even Parity, the Parity bit should be 1 if an odd
number of 1s in the Data bits is received; otherwise, the Parity bit should be 0. For
Odd Parity, the Parity bit should be 1 if an even number of 1s in the Data bits is
received; otherwise, the Parity bit should be 0. For Stick Parity '1', the Parity bit
should be 1. For Stick Parity '0', the Parity bit should be 0.
OE
PE
FE
Framing Error
FE will be reset to logic 0 whenever SIN is sampled high at the center of the first
Stop bit, regardless of how many Stop bits the UART is configured to.
BI
Break Interrupt
BI will be set to logic 1 whenever SIN is low for longer than the whole frame (the
time of Start bit + Data bits + Parity bit + Stop bits), not at the SIN rising edge where
Break is negated. If SIN is still low after BI is reset to logic 0 by reading LSR, BI will
not be set to logic 1 again. Since Break is also a Framing error, FE will also be set to
1 when BI is set.
THR Empty
THRE will be set to logic 1 whenever THR is empty which indicates that the
transmitter is ready to accept new data to transmit.
Both THR and TSR are Empty
This bit will be set to logic 1 when THRE is set to 1 and the last Data bit in the TSR
is shifted out through SOUT.
* The four error flags (OE, PE, FE and BI) of LSR will be reset to logic 0 after a LSR read.
Since the SIN and SOUT of UART pins are shared with PRTD[1..0], users can use the mask option to
enable the UART function and select PRTD[1..0] function.
0
PRTD[1:0] = I/O Pin
MO_UART
1
PRTD[1:0] = UART Pin
THRE
TEMT
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