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參數(shù)資料
| 型號： | HE83R540(S) |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 312K |
| 代理商： | HE83R540(S) |
King Billion Electronics Co., Ltd
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億
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子
股
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有
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公
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HE83R123
HE80000 Series
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded
with the value of T2H and T2L.
April 28, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
11
V1.0E
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value
of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when
system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and
value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value
should be set before enabling Timer2.
T2H
T2L
"Timer2 Counter"
decreases 1
Count TO
0xFFFFh
Auto reload when
Timer2 underflow
No
Start Timer2
Interrupt Request.
Yes
The contents of T2H and
T2L almost loaded into
Timer2 immediately
when Timer2 is turned on
after reset.
T2_INT
The Timer2 related control registers are list as below:
Register Address
Field
IER
0x02
TC2_IER
Bit position Mode
1
Description
R/W 0: TC2 interrupt is disabled. (default)
1: TC2 interrupt is enabled.
W
Low byte of TC2 pre-load value
W
High byte of TC2 pre-load value
R/W 0: TC2 is disabled. (default)
T2L
T2H
OP1
0x05
0x06
0x09
T2L[7:0]
T2H[7:0]
TC2E
7~0
7~0
3
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