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參數(shù)資料
| 型號： | HDSP2113S |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 8-Character 5x7 Dot Matrix Parallel Input Alphanumeric Intelligent Display |
| 中文描述： | 8個字符的5x7點陣并行輸入字母數(shù)字智能顯示器 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 509K |
| 代理商： | HDSP2113S |
2000 In
fi
neon Technologies Corp.
Optoelectronics Division
San Jose, CA
www.in
fi
neon.com/opto
1-888-In
fi
neon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG
Regensburg, Germany
www.osram-os.com
+49-941-202-7178
HDSP2110S/1S/2S/3S/4S/5S
8
March 24, 2000-13
Table 1. Memory Selection
FL
A4
A3
Theory of operation
The HDSP211XS Programmable Display is designed to work
with all major microprocessors. Data entry is via an eight bit
parallel bus. Three bits of address route the data to the proper
digit location in the RAM. Standard control signals like WR and
CE allow the data to be written into the display.
D0–D7 data bits are used for both Character RAM and control
word data input. A3 acts as the mode selector.
If A3=1, character RAM is selected. Then input data bit D7 will
determine whether input data bits D0–D6 is ASCII coded data
(D7=0) or UDC data (D7=1). See section on UDC Address Reg-
ister and RAM.
For normal operation FL pin should be held high. When FL is
held low, Flash RAM is accessed to set character blinking.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent
out each display cycle, and it takes fourteen display cycles to
write into eight digits.
The rows are multiplexed in two sets of seven rows each.
The internal timing and control logic synchronizes the turning
on of rows and presentation of column data to assure proper
display operation.
Power Up Sequence
Upon power up display will come on at random. Thus the dis-
play should be reset on power-up. The reset will clear the
Flash RAM, Control Word Register and reset the internal
counter. All the digits will show blanks and display brightness
level will be 100%.
The display must not be accessed until three clock pulses
(110
μ
seconds minimum using the internal clock) after the ris-
ing edge of the reset line.
Microprocessor interface
The interface to a microprocessor is through the 8-bit data
bus (D0–D7), the 4-bit address bus (A0–A3) and control lines
FL, CE and WR.
To write data (ASCII/Control Word) into the display CE should
be held low, address and data signals stable and WR should
be brought low. The data is written on the low to high transi-
tion of WR.
The Control Word is decoded by the Control Word Decode
Logic. Each code has a different function. The code for display
brightness changes the duty cycle for the column drivers. The
peak LED current stays the same but the average LED current
diminishes depending on the intensity level.
Section of Memory
A2–A0
Data Bits Used
0
X
X
Flash RAM
Character Address
D0
1
0
0
UDC Address Register
Don’t Care
D3–D0
1
0
1
UDC RAM
Row Address
D4–D0
1
1
1
Character RAM
Character Address
D7–D0
1
1
0
Control Word Register
Don’t Care
D7–D0
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with column drive signal and makes the
column driver to cycle at 2.0 Hz. Thus the character flashes at
2.0 Hz.
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby
making all eight digits to blink at 2.0 Hz.
The Self Test function of the IC consists of two internal rou-
tines which exercise major portions of the IC and illuminates
all the LEDs.
Clear bit clears the character RAM and writes a blank into the
display memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display
at this point. For multiple display operation, CLK I/O must be
properly selected. CLK I/O will output the internal clock if
CLKSEL=1, or will allow input from an external clock if
CLKSEL=0.
Character RAM
The Character RAM is selected when FL, A4 and A3 are set to
1,1,1 during a read or write cycle. The Character RAM is a 8 by
8 bit RAM with each of the eight locations corresponding to a
digit on the display. Digit 0 is on the left side of the display and
digit 7 is on the right side of the display. Address lines, A2–A0
select the digit address with A2 being the most significant bit
and A0 being the least significant bit. The two types of data
stored in the Character RAM are the ASCII coded data and the
UDC Address Data. The type of data stored in the Character
RAM is determined by data bit, D7. If D7 is low, then ASCII
coded data is stored in data bits D6–D0. If D7 is high, then UDC
Address Data is stored in data bit D3–D0.
The ASCII coded data is a 7 bit code used to select one of 128
ASCII characters permanently stored in the ASCII ROM.
The UDC Address data is a 4 bit code used to select one of the
UDC characters in the UDC RAM. There are up to 16 charac-
ters available. See Figure 8.
UDC Address Register and UDC RAM
The UDC Address Register and UDC RAM allows the user to
generate and store up to 16 custom characters. Each custom
character is defined in 5 x 7 dot matrix pattern. It takes 8 write
cycles to define a custom character, one cycle to load the UDC
Address Register and 7 cycles to define the character. The con-
tents of the UDC Address Register will store the 4 bit address
for one of the 16 UDC RAM locations. The UDC RAM is used
to store the custom character.
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