參數(shù)資料
型號: HDSP2111S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 8-Character 5x7 Dot Matrix Parallel Input Alphanumeric Intelligent Display
中文描述: 8個字符的5x7點陣并行輸入字母數(shù)字智能顯示器
文件頁數(shù): 2/13頁
文件大?。?/td> 509K
代理商: HDSP2111S
www.in
fi
neon.com/opto
1-888-In
fi
neon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG
Regensburg, Germany
www.osram-os.com
+49-941-202-7178
2000 In
fi
neon Technologies Corp.
Optoelectronics Division
San Jose, CA
HDSP2110S/1S/2S/3S/4S/5S
2
March 24, 2000-13
Maximum Ratings
(
T
A
=25
°
C)
DC Supply Voltage,
(max. voltage with no LEDs on)...................–0.3 to +7.0 VDC
Input Voltage Levels,
All Inputs.......................................................–0.3 to
Operating Temperature ....................................... –40
Storage Temperature......................................... –40
Relative Humidity (non-condensing)....................................85%
Operating Voltage,
V
CC
to GND
(Max. voltage with 20 dots/digits on)..............................5.5 V
Maximum Solder Temperature
(0.063" below seating plane, t<5.0 s)............................260
ESD Protection at 1.5 k
,
100 pF.....................................................V
V
CC
to GND
V
CC
+0.3
°
°
°
C to 100
C to 85
C
C
°
°
C
Z
=4.0 kV (each pin)
Figure 1. Enlarged Character Font
Dimensions in inches (mm)
Figure 2. Write Cycle Timing Diagram
Input pulse levels –0.6 V to 2.4 V
ESD Warning:
Standard precautions for CMOS
handling should be observed.
0.112
(2.85)
0.030 (0.76) Typ.
0.01 (0.254)
0.026 (0.65) Typ.
0.189
(4.81)
R1
R2
R3
R4
R5
R6
R7
C1 C2 C3 C4 C5
Tacc
Twd
Tdh
Tw
Tces
Tcer
Tceh
Tacs
Tach
Tacs
A0-A3
FL
Tce
CE
WR
D0-D7
Input pulse levels
0.6 V to 2.4 v
Switching Specifications
(over operating temperature range and
V
CC
=4.5 V)
Symbol
Description
Min.
Units
T
acc
Display Access Time—Write
210
ns
T
acc
Display Access Time—Read
230
ns
T
acs
Address Setup Time to CE
T
ce
Chip Enable Active Time—Write
140
ns
T
ce
Chip Enable Active Time—Read
160
ns
T
ach
Address Hold Time to CE
T
cer
Chip Enable Recovery Time
60
ns
T
ces
Chip Enable Active Prior to
Rising Edge—Write
140
ns
T
ces
Chip Enable Active Prior to
Rising Edge—Read
160
ns
T
ceh
Chip Enable Hold to Rising Edge
of Read/Write Signal
0
ns
T
w
Write Active Time
100
ns
T
wd
Data Valid Prior to
Rising Edge of Write Signal
50
ns
T
dh
Data Write Time
20
ns
T
r
Chip Enable Active Prior to Valid
Data
160
ns
T
rd
Read Active Prior to Valid Data
95
T
df
Read Data Float Delay
10
ns
T
rc
Reset Active Time
300
ns
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