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參數(shù)資料
| 型號： | HDSP-2179 |
| 英文描述： | Eight Character 5.0 mm (0.2 inch) Glass/Ceramic Intelligent 5 x 7 Alphanumeric Displays for Military Applications(軍用的八字符5.0 mm (0.2英寸)玻璃/陶瓷智能 5 x 7文字數(shù)字顯示器) |
| 中文描述： | 八字5.0毫米（0.2英寸）玻璃/陶瓷智能5 × 7的軍事應用字母數(shù)字顯示器（軍用的八字符5.0毫米（0.2英寸）玻璃/陶瓷智能5 × 7文字數(shù)字顯示器） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 319K |
| 代理商： | HDSP-2179 |
6
AC Timing Characteristics over Temperature Range
V
DD
= 4.5 to 5.5 V unless otherwise specified.
Reference
Number
Symbol
Description
Min.
[1]
Units
1
t
ACC
Display Access Time
Write
Read
210
230
ns
2
t
ACS
Address Setup Time to Chip Enable
10
ns
3
t
CE
Chip Enable Active Time
[2, 3]
Write
Read
140
160
ns
4
t
ACH
Address Hold Time to Chip Enable
20
ns
5
t
CER
Chip Enable Recovery Time
60
ns
6
t
CES
Chip Enable Active Prior to Rising Edge of
[1,2]
Write
Read
140
160
ns
7
t
CEH
Chip Enable Hold Time to Rising Edge of
Read/Write Signal
[2, 3]
0
ns
8
t
W
Write Active Time
[2,3]
100
ns
9
t
WD
Data Valid Prior to Rising Edge of Write Signal
50
ns
10
t
DH
Data Write Hold Time
20
ns
11
t
R
Chip Enable Active Prior to Valid Data
160
ns
12
t
RD
Read Active Prior to Valid Data
75
ns
13
t
DF
Read Data Float Delay
10
ns
t
RC
Reset Active Time
[4]
300
ns
Notes:
1. Worst case values occur at an IC junction temperature of 150
°
C.
2. For designers who do not need to read from the display, the Read line can be tied to V
DD
and the Write and Chip Enable lines can be
tied together.
3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM,
regardless of the logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110
μ
s min. using the internal refresh clock) after the rising edge of the
reset line.
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相關代理商/技術參數(shù) |
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|---|---|
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