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參數(shù)資料
| 型號(hào)： | HD74SSTV16857 |
| 英文描述： | Datasheet|ADE-205-336F|JUN.20.01|125K |
| 中文描述： | 技術(shù)資料|腺- 205 - 336F章| JUN.20.01 | 125K |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 47K |
| 代理商： | HD74SSTV16857 |
HD74SSTL16857
14-bit SSTL_2 Registered Buffer
ADE-205-223C (Z)
4th. Edition
May 1999
Description
The HD74SSTL16857 is a 14-bit registered buffer designed for 2.3 V to 3.6 V Vcc operation and LVCMOS
reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered
on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise
margins. When RESET is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
Features
Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Flow through architecture optimizes PCB layout
Meets SSTL_2 Class I and Class II specifications
Function Table
H :
L :
X :
↑
:
↓
:
High level
Low level
Immaterial
Low to high transition
High to low transition
Note:
1.Output level before the indicated steady state input conditions were established.
Inputs
RESET
L
H
H
H
Output Q
CLK
X
↓
↓
L or H
CLK
X
↑
↑
H or L
D
X
H
L
X
L
H
L
Q
0
*1
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參數(shù)描述 |
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