參數(shù)資料
型號(hào): HD74LV2GT245A
廠商: Renesas Technology Corp.
英文描述: Dual Bus Transceivers with 3?state Outputs / CMOS Logic Level Shifter
中文描述: 3?國家輸出/ CMOS邏輯電平轉(zhuǎn)換器雙總線收發(fā)器
文件頁數(shù): 1/10頁
文件大小: 96K
代理商: HD74LV2GT245A
Rev.2.00, Oct.23.2003, page 1 of 9
HD74LV2GT245A
Dual Bus Transceivers with 3–state Outputs /
CMOS Logic Level Shifter
REJ03D0153–0200Z
(Previous ADE-205-694A (Z))
Rev.2.00
Oct.23.2003
Description
The HD74LV2GT245A has two buffers with three state output in a 8 pin package. When DIR is high, data
is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs
to the A outputs. The A and B buses are separated by making the enable input (
OE
) high level. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic
5.0 V CMOS logic (@V
CC
= 5.0 V)
1.8 V or 2.5 V CMOS logic
3.3 V CMOS logic (@V
CC
= 3.3 V)
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V, Output : Z)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LV2GT245AUSE
SSOP-8 pin
TTP-8DBV
US
E (3,000 pcs/reel)
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