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參數(shù)資料
| 型號(hào)： | HD74LV161A |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-bit Binary Counter (Direct Clear)(同步4位二進(jìn)制計(jì)數(shù)器) |
| 中文描述： | 同步4位二進(jìn)制計(jì)數(shù)器（直接清除）（同步4位二進(jìn)制計(jì)數(shù)器） |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 84K |
| 代理商： | HD74LV161A |
HD74LV161A
9
Switching Characteristics (cont)
V
CC
= 3.3
±
0.3 V
Ta = 25
°
C
Ta = –40 to 85
°
C
Item
Symbol
Min
Typ
Max
Min
Max
Unit
Test Conditions
FROM
(Input)
TO
(Output)
Maximum
clock
frequency
fmax
80
130
—
70
—
MHz
C
L
= 15 pF
55
85
—
50
—
C
L
= 50 pF
Propa-
gation
delay time
t
PLH
/t
PHL
—
8.3
12.8
1.0
15.0
ns
C
L
= 15 pF
CLK
Q
—
10.8
16.3
1.0
18.5
C
L
= 50 pF
t
PLH
/t
PHL
—
8.7
13.6
1.0
16.0
C
L
= 15 pF
CLK
Carry
Count
mode
—
11.2
17.1
1.0
19.5
C
L
= 50 pF
t
PLH
/t
PHL
—
11.0
17.2
1.0
20.0
C
L
= 15 pF
CLK
Carry
Load
mode
—
13.5
20.7
1.0
23.5
C
L
= 50 pF
t
PLH
/t
PHL
—
7.5
12.3
1.0
14.5
C
L
= 15 pF
ENT
Carry
—
10.5
15.8
1.0
18.0
C
L
= 50 pF
t
PHL
—
8.9
13.6
1.0
16.0
C
L
= 15 pF
CLR
Q
—
11.2
17.1
1.0
19.5
C
L
= 50 pF
t
PHL
—
8.4
13.2
1.0
15.5
C
L
= 15 pF
CLR
Carry
—
10.9
16.7
1.0
19.0
C
L
= 50 pF
Setup time
t
su
5.5
—
—
6.5
—
ns
Data before CLK
↑
8.0
—
—
9.5
—
LOAD
before CLK
↑
7.5
—
—
9.0
—
ENT, ENP before CLK
↑
2.5
—
—
2.5
—
CLR
inactive before
CLK
↑
Hold time
t
h
1.0
—
—
1.0
—
ns
Pulse
width
t
w
5.0
—
—
5.0
—
ns
CLK H or L
5.0
—
—
5.0
—
CLR
L
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