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參數(shù)資料
| 型號： | HD74LS280FPEL |
| 元件分類： | 算術邏輯單元 |
| 英文描述： | LS SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 5.50 X 10.06 MM, 1.27 MM PITCH, PLASTIC, SOP-14 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 175K |
| 代理商： | HD74LS280FPEL |
Rev.3.00, Jul.15.2005, page 1 of 5
HD74LS280
9-bit Odd / Even Parity Generator / Checker
REJ03D0475–0300
Rev.3.00
Jul.15.2005
This parity generator / checker offers the designer a trade-off between reduced power consumption and high
performance. Although the HD74LS280 is implemented without expander inputs, the corresponding function is
provided by the availability of an input at pin 4 and the absence of any internal connection at pin 3.
Features
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS280P
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
—
HD74LS280FPEL
SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
EL (2,000 pcs/reel)
Notes: Please consult the sales office for the above package availability.
Pin Arrangement
(Top view)
GND
1
2
3
4
5
6
7
14
8
9
10
11
12
13
G
H
NC
Input I
A
Σ
Even
Σ
Odd
Σ Odd
VCC
F
G
E
D
B
F
C
I
H
Σ Even
A
B
Inputs
Outputs
Function Table
Outputs
Number of inputs A through I that are high
Σ Even
Σ Odd
0, 2, 4, 6, 8
H
L
1, 3, 5, 7, 9
L
H
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相關代理商/技術參數(shù) |
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| HD74LS283P | 制造商:Renesas Electronics 功能描述:74LS |
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