參數(shù)資料
型號: HD74HC137
廠商: Hitachi,Ltd.
元件分類: 通用總線功能
英文描述: Synchronous 4-Bit Up/Down Binary Counters With Dual Clock 16-CFP -55 to 125
中文描述: 3至8線解碼器/解復(fù)用器的地址鎖存器
文件頁數(shù): 1/10頁
文件大?。?/td> 60K
代理商: HD74HC137
HD74HC137
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When
GL
goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As
long as
GL
remains high no address changes will be recognized. Output enable controls, G
1
and G
2
, control
the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are high unless G
1
is high and G
2
is low. The HD74HC137 is ideally suited for the
implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
High Speed Operation: t
pd
(A, B, C to Y) = 16.5 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 V to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
相關(guān)PDF資料
PDF描述
HD74HC138 3-to-8-line Decoder/Demultiplexer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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