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參數(shù)資料
| 型號： | HD74HC107 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dual J-K Flip-Flops (with Clear) |
| 中文描述： | 雙JK觸發(fā)器（帶透明） |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 57K |
| 代理商： | HD74HC107 |
HD74HC107
4
AC Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Ta = 25
°
C
Ta = –40 to
+85
°
C
Item
Symbol
V
CC
(V)
2.0
Min Typ Max Min
Max
Unit
Test Conditions
Maximum clock
f
max
—
—
6
—
5
MHz
frequency
4.5
—
—
30
—
24
6.0
—
—
35
—
28
Propagation delay t
PLH
time
2.0
—
—
150 —
190
ns
Clock to Q or
Q
t
PHL
4.5
—
19
30
—
38
6.0
—
—
26
—
33
2.0
—
—
140 —
175
ns
Clear to Q or
Q
4.5
—
17
28
—
35
6.0
—
—
24
—
30
Pulse width
t
w
2.0
80
—
—
100
—
ns
Clock, Clear
4.5
16
7
—
20
—
6.0
14
—
—
17
—
Setup time
t
su
2.0
100 —
—
125
—
ns
J or K to Clock
4.5
20
3
—
25
—
6.0
17
—
—
21
—
Hold time
t
h
2.0
5
—
—
5
—
ns
Clock to J or K
4.5
5
–2
—
5
—
6.0
5
—
—
5
—
Removal time
t
rem
2.0
100 —
—
125
—
ns
Clear to Clock
4.5
20
0
—
25
—
6.0
17
—
—
21
—
Output rise/fall
t
TLH
t
THL
2.0
—
—
75
—
95
ns
time
4.5
—
5
15
—
19
6.0
—
—
13
—
16
Input capacitance
Cin
—
—
5
10
—
10
pF
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PDF描述 |
|---|---|
| HD74HC108 | Synchronous 4-Bit Up/Down Binary Counter 16-CDIP -55 to 125 |
| HD74HC109 | Dual J-K Flip-Flops (with Preset and Clear) |
| HD74HC10 | Triple 3-input NAND Gates |
| HD74HC112 | Dual J-K Flip-Flops (with Preset and Clear) |
| HD74HC113 | Dual J-K Flip-Flops (with Preset) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74HC107FP | 制造商:Renesas Electronics 功能描述:74HC Dual J-K Flip-Flop with Clear |
| HD74HC109P-E | 制造商:Renesas Electronics 功能描述:74HC Dual J-K Flip-Flop with Preset and Clear |
| HD74HC10P-E | 制造商:Renesas Electronics Corporation 功能描述: |
| HD74HC10P-E-Q | 制造商:Renesas Electronics Corporation 功能描述:ANALOG IC |
| HD74HC112FP | 制造商:Renesas Electronics Corporation 功能描述:Flip Flop JK-Type Neg-Edge 2-Element 16-Pin SOP |
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