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參數(shù)資料
| 型號(hào)： | HD74CDC2509B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 的3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器（3.3 V的鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 42K |
| 代理商： | HD74CDC2509B |
HD74CDC2509B
3.3-V Phase-lock Loop Clock Driver
ADE-205-218F (Z)
7th. Edition
October 1999
Description
The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
HD74CDC2509B operates at 3.3 V V
CC
and is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input
clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the
G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the
outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDC2509B does not require external RC networks. The
loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDC2509B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV
CC
to ground.
Features
Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
Phase-lock loop clock distribution for synchronous DRAM applications
External feedback (FBIN) pin is used to synchronize the outputs to the clock input
No external RC network required
Support spread spectrum clock (SSC) synthesizers
Note:
Only by a change of a suffix (A to B) for standardization, there isn’t any change of the product.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD74CDC2509 | 3.3-V Phase-lock Loop Clock Driver(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| HD74CDC2510B | 3.3-V Phase-lock Loop Clock Driver(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| HD74CDC587 | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| HD74CDC857 | 3.3/2.5-V Phase-lock Loop Clock Driver |
| HD74CDCF2509B | 3.3-V Phase-lock Loop Clock Driver(3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74CDC2509BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDC2510BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2509BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2510BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
| HD74CDCF2510BTEL-E | 制造商:Renesas Electronics Corporation 功能描述:PLL CLOCK DRIVERS - Tape and Reel |
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