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參數(shù)資料
| 型號(hào)： | HD74CDC2509 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 的3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器（3.3 V的鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 52K |
| 代理商： | HD74CDC2509 |
HD74CDC2509
7
Switching Characteristics
(C
L
= 30 pF)
Item
Symbol V
CC
= 3.3 V
±
0.165 V V
CC
= 3.3 V
±
0.3 V
Min
Typ
Max
Unit
From (Input)
To (Output)
Min
Typ
Max
Phase error time
t
pe
—
—
—
—
-0.7~0.1
—
ns
66 MHz <
CLKIN
↑
<
100 MHz
FBIN
↑
Phase error time –
jitter
*2
–500
—
–50
—
–310
—
ps
CLKIN
↑
=100 MHz
FBIN
↑
Between output pins
skew
*1
t
sk (O)
—
—
—
—
—
200
ps
Any Y or
FBOUT
Any Y or
FBOUT
Jitter
—
—
—
–100 —
100
ps
F (clkin >
66 MHz)
Any Y or
FBOUT
Duty cycle
—
—
—
45
—
55
%
F (clkin
≤
66 MHz)
Any Y or
FBOUT
—
—
—
43
—
55
F (clkin >
66 MHz)
Any Y or
FBOUT
Output rise / fall time t
TLH
—
1.3
1.9
0.8
—
2.1
ns
Any Y or
FBOUT
t
THL
—
1.7
2.3
1.2
—
2.5
Any Y or
FBOUT
Notes:
The specifications for parameters in this table are applicable only after any appropriate
stabilization time has elapsed.
1. The t
sk(O)
specification is only valid for equal loading of all outputs.
2. Phase error does not include jitter. The total phase error is –600 ps to +50 ps for the 5% V
CC
range.
Timing requirements
Item
Symbol Min
Max
Unit
Test Conditions
Input clock frequency
f
clock
25
125
MHz
Input clock duty cycle
40
60
%
Stabilization time
*1
Note:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay and skew parameters given in the switching characteristics table are not
applicable.
—
1
ms
After power up
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|---|---|
| HD74CDC2509BTEL | 制造商:Renesas Electronics Corporation 功能描述:FACT - Tape and Reel |
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