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參數(shù)資料
| 型號(hào)： | HD74ALVCH162501 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 18-bit Universal Bus Transceivers with 3-state Outputs(三態(tài)輸出的18位通用總線收發(fā)器) |
| 中文描述： | 18位通用總線收發(fā)器具有三態(tài)輸出（三態(tài)輸出的18位通用總線收發(fā)器） |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大小： | 53K |
| 代理商： | HD74ALVCH162501 |
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HD74ALVCH162501
18-bit Universal Bus Transceivers with 3-state Outputs
ADE-205-182 (Z)
Preliminary
1st. Edition
December 1996
Description
Data flow in each direction is controlled by output enable (OEAB and
OEBA
), latch enable (LEAB
and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is stored in the latch flip flop on the low to
high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the
outputs are in the high impedance state. Data flow for B to A is similar to that of A to B but uses
OEBA
, LEBA, and CLKBA. The output enables are complementary (OEAB is active high, and
OEBA
is active low). Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level. All outputs, which are designed to sink up to 12 mA, include 26
resistors to reduce
overshoot and undershoot.
Features
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
High output current ±12 mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
All outputs have equivalent 26
series resistors, so no external resistors are required.
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| HD74ALVCH162543 | 16-bit Registered Transceivers with 3-state Outputs(三態(tài)輸出的16位寄存收發(fā)器) |
| HD74ALVCH16260 | 12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs(三態(tài)輸出的12位至24位多重D鎖存器) |
| HD74ALVCH16269 | 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs(三態(tài)輸出的12位至24位寄存總線收發(fā)器) |
| HD74ALVCH16270 | 12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs(三態(tài)輸出的12位至24位寄存總線交換器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74ALVCH162543 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:16-bit Registered Transceivers with 3-state Outputs |
| HD74ALVCH16260 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:12-bit to 24-bit Multiplexed D-type Latches with 3-state Outputs |
| HD74ALVCH16269 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs |
| HD74ALVCH16270 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:12-bit to 24-bit Registered Bus Exchanger with 3-state Outputs |
| HD74ALVCH162721 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:3.3-V 20-bit Flip Flops with 3-state Outputs |
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