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參數(shù)資料
| 型號： | HD74AC273 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Triple 3-Input Positive-AND Gates 14-CFP -55 to 125 |
| 中文描述： | 八路D觸發(fā)器 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 60K |
| 代理商： | HD74AC273 |
HD74AC273
Octal D Flip-Flop
Description
The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (
MR
) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High
clock transition, is transferred to the corresponding flip-flops’s Q output
All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the
MR
input. The device is useful for applications where the true output only is required and the Clock and Master
Reset are common to all storage elements.
Features
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See HD74AC373 for Transparent Latch Version
See HD74AC374 for 3-State Version
Outputs Source/Sink 24 mA
相關PDF資料 |
PDF描述 |
|---|---|
| HD74AC283 | Octal Buffers And Drivers With 3-State Outputs 20-CDIP -55 to 125 |
| HD74ACT283 | 3-Line To 8-Line Decoders/Demultiplexers 16-CDIP -55 to 125 |
| HD74AC32 | Octal Buffers And Drivers With 3-State Outputs 20-LCCC -55 to 125 |
| HD74AC365 | Octal Buffers And Drivers With 3-State Outputs 20-CDIP -55 to 125 |
| HD74ACT365 | 3-Line To 8-Line Decoders/Demultiplexers 16-CFP -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HD74AC273FP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
| HD74AC273FPEL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Octal D-Type Flip-Flop |
| HD74AC273P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
| HD74AC273RPEL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Octal D-Type Flip-Flop |
| HD74AC280 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:9-bit Parity Generator/Checker |
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