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參數(shù)資料
| 型號(hào)： | HD74AC174T |
| 元件分類： | 鎖存器 |
| 英文描述： | D FLIP-FLOP, PDSO16 |
| 封裝： | TTP-16DA |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大?。?/td> | 54K |
| 代理商： | HD74AC174T |
HD74AC174
2
Logic Symbol
D0 D1 D2
D3 D4
D5
Q0
CP
MR
Q1 Q2
Q3 Q4
Q5
Pin Names
D
0 to D5
Data Inputs
CP
Clock Pulse Input
MR
Master Reset Input
Q
0 to Q5
Outputs
Functional Description
The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The
Clock (CP) and Master Reset (
MR) are common to all flip-flops. Each D input’s state is transferred to the
corresponding flip-flops’s output following the Low-to-High Clock (CP) transition. A Low input to the
Master Reset (
MR) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is
useful for applications where the true output only is required and the Clock and Master Reset are common
to all storage elements.
Truth Table
Inputs
Output
MR
CP
D
Q
LX
X
L
H
HH
H
LL
H
LXQ
H :
High Voltage Level
L
:
Low Voltage Level
X :
Immaterial
:
Low-to-High Transition of Clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD74HC149FP | HC/UH SERIES, 8-BIT ENCODER, PDSO20 |
| HD74LS367 | Dual High-Voltage, High-Current Peripheral Drivers 8-PDIP 0 to 70 |
| HD74LS367A | Dual High-Voltage, High-Current Peripheral Drivers 8-PDIP 0 to 70 |
| HD74LS368A | Hex Bus Drivers(inverted data outputs with three-state outputs) |
| HD74LS373 | Dual High-Voltage, High-Current Peripheral Drivers 8-PDIP 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD74AC175 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Quad D-Type Flip-Flop |
| HD74AC175AFPEL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad D-Type Flip-Flop |
| HD74AC175ARPEL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Quad D-Type Flip-Flop |
| HD74AC175FP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
| HD74AC175FP-E | 制造商:Renesas Electronics 功能描述:Cut Tape |
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