參數(shù)資料
型號： HD66731A01TA0L
廠商： Hitachi,Ltd.
英文描述： Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display
中文描述： 點陣液晶顯示控制器/驅(qū)動器支持日語漢字，韓文字體顯示
文件頁數(shù)： 16/131頁
文件大小： 5332K
代理商： HD66731A01TA0L
HD66730/HD66731
16
Function Description
System Interface
The HD66730/1 has two system interfaces: a synchronized serial one and an 8-bit bus. Both are selected by
the IM pin.
The HD66730/1 has five types of 8-bit registers: an index register (IDR), status register (STR), various
control registers, RAM address register (RAR), and RAM data register (RDR).
The index register (IDR) selects control registers, the RAM address register (RAR) or the RAM data
register (RDR) for performing data transfer.
The status register (STR) indicates the internal state of the system. Various control registers store display
control data here.
The RAM address register (RAR) stores the address data of display data RAM (DDRAM), character
generator RAM (CGRAM), and segment RAM (SEGRAM).
The RAM data register (RDR) temporarily stores data to be written into DDRAM, CGRAM, or SEGRAM.
Data written into the RDR from the MPU is automatically written into DDRAM, CGRAM, or SEGRAM
by internal operations. The RDR is also used for data storage when reading data from DDRAM, CGRAM,
or SEGRAM. Here, when address information is written into the RAR, data is read and then stored into the
RDR from DDRAM, CGRAM, or SEGRAM by internal operations.
Data transfer between the MPU is then completed when the MPU reads the RDR. After this read, data in
DDRAM, CGRAM, or SEGRAM stored at the next address is sent to the RDR at the next data read from
the MPU.
These registers can be selected by the register select signal (RS) and the read/write signal (R/W) in the 8-bit
bus interface, and by the RS bit and R/W bit of start-byte data in the synchronized serial interface.
Busy Flag
When the busy flag is 1, the HD66730/1 is in internal operation mode, and only the status register (STR)
can be accessed. The busy flag (BF) is output from bit 7 (DB7). Access of other registers can be performed
only after confirming that the busy flag is 0.
RAM Address Counter (RAR)
The RAM address counter (RAR) provides addresses for accessing DDRAM, CGRAM, or SEGRAM.
When an initial address value is written into the RAM counter (RAR), the RAR is automatically
incremented or decremented by 1. Note that a control register specifies which RAM (DDRAM, CGRAM,
SEGRAM) to select.
相關(guān)PDF資料
PDF描述
HD66731A01TB0L Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HD66731A01TB0L 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display
HD66732 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:Hraphics Liquid Crystal Display Controller/Driver Supportiong JIS Level-1 and Level-2 Kangi ROM)
HD66735 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HD66735 Procedure for setting Standby/Sleep/Display off mode. Technical Update/Device
HD66740 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
HD66740TB0 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:112 x 80-dot Graphics LCD Controller/Driver
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