
HD66724/HD66725
59
Key Scan Control
The key matrix scanner senses and holds the key states at each rising edge of key strobe signals (KST) that
are output by the HD66724/HD66725. The key strobe signals are output as time-multiplexed signals from
KST0 to KST3. After passing through the key matrix, these strobe signals are used to sample the key state
of eight inputs KIN0 to KIN7, enabling up to 32 keys to be scanned.
The states of inputs KIN0 to KIN7 are sampled by key strobe signal KST0 and latched into the SCAN0
register. Similarly, the data sampled by strobe signals KST1 to KST3 is latched into the SCAN1 to SCAN3
registers, respectively. Key pressing is stored as 1 in these registers.
The generation cycle and pulse width of the key strobe signals depend on the operating frequency
(oscillation frequency) of the HD66724/HD66725 and the key scan cycle determined by the KF0 and KF1
bits. For example, when the operating frequency is 32 kHz and KF0 and KF1 are both 10, the generation
cycle is 4.0 ms and the pulse width is 1.0 ms. When the operating frequency (oscillation frequency) is
changed, the above generation cycle and the pulse width are changed in inverse proportion.
In order to compensate for the mechanical features of the keys, such as chattering and noise and for the
key-strobe generation cycle and the pulse width of the HD66724/HD66725, software should read the
scanned data two to three times in succession to obtain valid data. Multiple keypress combinations should
also be processed in the software.
Up to three keys can be pressed simultaneously. Note, however, that if the third key is pressed on the
intersection between the rows and columns of the first two keys pressed, incorrect data will be sampled. For
three-key input, the third key must be on a separate column or row.
The input pins KIN0 to KIN7 are pulled up to V
CC
with internal MOS transistors (see the Electrical
Characteristics section). External resistors may also be required to further pull the voltages up when the
internal pull-ups are insufficient for the desired noise margins or for a large key matrix.
SCAN0
SCAN1
SCAN2
SCAN3
D
03
D
02
D
01
D
00
D
13
D
12
D
11
D
10
D
23
D
22
D
21
D
20
D
33
D
32
D
31
D
30
KIN3 KIN2 KIN1 KIN0
(KST0
↑)
(KST1
↑)
(KST2
↑)
(KST3
↑)
D
04
D
14
D
24
D
34
KIN4
D
05
D
15
D
25
D
35
KIN5
D
06
D
16
D
26
D
36
KIN6
D
07
D
17
D
27
D
37
KIN7
KSD7 KSD6KSD5 KSD4KSD3 KSD2KSD1 KSD0
Figure 26 Key Scan Register Configuration