- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370470 > HD66324T (Hitachi,Ltd.) 64-level Grayscale Driver for the High-Quality TFT Liquid Crystal Display for XGA/SXGA Systems(高品質(zhì)TFT LCD的64級灰度驅(qū)動器) PDF資料下載
參數(shù)資料
| 型號： | HD66324T |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64-level Grayscale Driver for the High-Quality TFT Liquid Crystal Display for XGA/SXGA Systems(高品質(zhì)TFT LCD的64級灰度驅(qū)動器) |
| 中文描述： | 64級灰度驅(qū)動的高品質(zhì)TFT液晶顯示技術(shù)的XGA / SXGA系統(tǒng)（高品質(zhì)TFT液晶顯示器的64級灰度驅(qū)動器） |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 336K |
| 代理商： | HD66324T |
HD66324
8
Operation Timing
CL2
EIO1
D5j
D4j
D3j
D2j
D1j
D0j
POL2
CL1
EIO2
(NO. 1)
EIO2
(NO. 8)
Y1 to Y384
1
2
512
513
3
62
63
64
65
d3840
INVALID
d12
d6
d18
d366 d372
d378
d384 d390
d3822 d3828 d3834 d3840
INVALID
IC (No. 8) data latch period
IC (No. 2) data latch period
IC (No. 1) data latch period
Line
When SHL = V
CC.
510
511
512
513
514
d3839
INVALID
d11
d5
d17
d365 d371
d377
d383 d389
d3821 d3827 d3833 d3839
INVALID
d3838
INVALID
d10
d4
d16
d364 d370
d376
d382 d388
d3820 d3826 d3832 d3838
INVALID
d3837
INVALID
d9
d3
d15
d363 d369
d375
d381 d387
d3819 d3825 d3831 d3837
INVALID
d3836
INVALID
d8
d2
d14
d362 d368
d374
d380 d386
d3818 d3824 d3830 d3836
INVALID
d3835
INVALID
d7
d1
d13
d361 d367
d373
d379 d385
d3817 d3823 d3829 d3835
INVALID
INVALID
INVALID
RESET
Figure 5 Operation Timing
The high level of the enable-input signal (when SHL = V
CC
: EIO1) is latched at the rising edge of the data-
latch clock signal CL2, and data latching begins after one CL2 signal cycle. Data of 6 bits
×
RGB
×
2
pixels, i.e. 6 outputs are simultaneously latched at the rising edge of the CL2 signal. At the rising edge of
the 64th clock pulse of the CL2 signal, the enable-output signal (when SHL = V
CC
: EIO2) is driven high,
and the operation is automatically halted (the standby state is entered) when latching of data for 384 outputs
is completed. By connecting the EIO2 pin to the next-stage EIO1 pin, the next-stage IC is activated in the
same way. All the IC enable-output signals are reset at the rising edge of the CL1 signal.
The data latch clock signal CL2 does not require a clock-halted period. At least two clocks must be added
to the necessary CL2 clocks (512 clocks for XGA) in each horizontal period.
Relationship between M Signal and Data Input
This example shows the relationship between the data input, M signal, and output level, with dot-by-dot
inversion and frame inversion. The HD66324T driver must hold the M signal during the high-level period
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD66325A | 64-level Grayscale Driver for the TFT Liquid Crystal Display for XGA Systems(高品質(zhì)TFT LCD的64級灰度驅(qū)動器) |
| HD66326T | Multiscan XGA/SXGA High-Quality 64-Gradation TFT Liquid Crystal Driver(TFT LCD驅(qū)動器) |
| HD66330T | 64-Level Gray Scale Driver for TFT Liquid Crystal Display(TFT LCD的64級灰度驅(qū)動器) |
| HD66350T | 256-level Grayscale TFT for XGA/SXGA/UXGA Systems(高品質(zhì)TFT LCD的256級灰度驅(qū)動器) |
| HD66410 | RAM-Provided 128-Channel Driver for Dot-Matrix Graphic LCD(點(diǎn)陣圖形LCD128通道驅(qū)動器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD66326T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| HD66330T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| HD66330TA0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| HD66339 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HD66410 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。