參數(shù)資料
型號(hào): HD66120T
廠商: Hitachi,Ltd.
英文描述: 240-Channel Segment Driver for Dot-Matrix Graphic Liquid Crystal Display(用于點(diǎn)陣圖形LCD的240通道段碼驅(qū)動(dòng)器)
中文描述: 240通道段驅(qū)動(dòng)的點(diǎn)陣圖形液晶顯示屏(用于點(diǎn)陣圖形液晶顯示的240通道段碼驅(qū)動(dòng)器)
文件頁(yè)數(shù): 16/21頁(yè)
文件大小: 77K
代理商: HD66120T
HD66120T
16
AC Characteristics 1 (V
CC
= 2.7 to 4.5V, VLCD–GND = 14 to 40V, and Ta = –30 to +75
°
C, unless
otherwise noted)
Item
Clock cycle time
Clock high-level width 1
Clock low-level width 1
Clock high-level width 2
Clock setup time
Clock hold time
Clock rise time
Clock fall time
Data setup time
Data hold time
M phase difference time
Output delay time 1
Output delay time 2
Notes at the end of the AC characteristics 2 table.
Symbol
t
CYC
t
CWH2
t
CWL2
t
CWH1
t
SCL
t
HCL
t
r
t
f
t
DS
t
DH
t
CM
t
pd1
t
pd2
Pins
CL2
CL2
CL2
CL1
CL1, CL2
CL1, CL2
CL1, CL2
CL1, CL2
D0–D7, CL2
D0–D7, CL2
M, CL1
CL1, Y1–Y240
M, Y1–Y240
Min
100
37
37
50
100
100
35
35
Max
50*
1
50*
1
300
1.2
1.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
AC Characteristics 2 (V
CC
= 5V
±
10%, VLCD–GND = 14 to 40V, and Ta = –30 to +75
°
C, unless
otherwise noted)
Item
Clock cycle time
Clock high-level width 1
Clock low-level width 1
Clock high-level width 2
Clock setup time
Clock hold time
Clock rise time
Clock fall time
Data setup time
Data hold time
M phase difference time
Output delay time 1
Output delay time 2
Notes: 1. The clock rise and fall times (t
r
, t
f
) must satisfy the following relationships:
t
r
, t
f
< (t
CYC
– t
CWH2
– t
CWL2
)/2
t
r
, t
f
50 ns
2. The load must be less than 30 pF between the
EIO2
and
EIO1
connections of HD66120Ts.
Symbol
t
CYC
t
CWH2
t
CWL2
t
CWH1
t
SCL
t
HCL
t
r
t
f
t
DS
t
DH
t
CM
t
pd1
t
pd2
Pins
CL2
CL2
CL2
CL1
CL1, CL2
CL1, CL2
CL1, CL2
CL1, CL2
D0–D7, CL2
D0–D7, CL2
M, CL1
CL1, Y1–Y240
M, Y1–Y240
Min
50
15
15
15
100
100
5
15
Max
50*
1
50*
1
300
0.7
0.7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
μ
s
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