Rev. 2.0, 03/02, Page ix of xxii
Section 7 ROM..............................................................................................75
7.1
Block Configuration.....................................................................................................75
7.2
Register Descriptions...................................................................................................76
7.2.1
Flash Memory Control Register 1 (FLMCR1)..................................................77
7.2.2
Flash Memory Control Register 2 (FLMCR2)..................................................78
7.2.3
Erase Block Register 1 (EBR1)........................................................................78
7.2.4
Flash Memory Enable Register (FENR)...........................................................79
7.3
On-Board Programming Modes....................................................................................79
7.3.1
Boot Mode ......................................................................................................80
7.3.2
Programming/Erasing in User Program Mode ..................................................82
7.4
Flash Memory Programming/Erasing ...........................................................................83
7.4.1
Program/Program-Verify.................................................................................83
7.4.2
Erase/Erase-Verify...........................................................................................85
7.4.3
Interrupt Handling when Programming/Erasing Flash Memory.........................86
7.5
Program/Erase Protection.............................................................................................88
7.5.1
Hardware Protection........................................................................................88
7.5.2
Software Protection .........................................................................................88
7.5.3
Error Protection...............................................................................................88
Section 8 RAM..............................................................................................89
Section 9 I/O Ports.........................................................................................91
9.1
Port 1...........................................................................................................................91
9.1.1
Port Mode Register 1 (PMR1)..........................................................................92
9.1.2
Port Control Register 1 (PCR1)........................................................................93
9.1.3
Port Data Register 1 (PDR1)............................................................................93
9.1.4
Port Pull-Up Control Register 1 (PUCR1)........................................................94
9.1.5
Pin Functions...................................................................................................94
9.2
Port 2...........................................................................................................................96
9.2.1
Port Control Register 2 (PCR2)........................................................................96
9.2.2
Port Data Register 2 (PDR2)............................................................................97
9.2.3
Pin Functions...................................................................................................97
9.3
Port 5...........................................................................................................................98
9.3.1
Port Mode Register 5 (PMR5)..........................................................................99
9.3.2
Port Control Register 5 (PCR5)........................................................................100
9.3.3
Port Data Register 5 (PDR5)............................................................................100
9.3.4
Port Pull-Up Control Register 5 (PUCR5)........................................................101
9.3.5
Pin Functions...................................................................................................101
9.4
Port 7...........................................................................................................................103
9.4.1
Port Control Register 7 (PCR7)........................................................................104
9.4.2
Port Data Register 7 (PDR7)............................................................................104
9.4.3
Pin Functions...................................................................................................105
9.5
Port 8...........................................................................................................................106